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dc.contributor.authorGruber, M.
dc.contributor.authorDesch, K.
dc.contributor.authorHemperek, T.
dc.contributor.authorKaminski, J.
dc.contributor.authorRicharz, Leonie Caroline
dc.contributor.authorSchiffer, T.
dc.date.accessioned2023-03-13T09:14:16Z
dc.date.available2023-03-13T09:14:16Z
dc.date.created2022-05-15T12:01:07Z
dc.date.issued2022
dc.identifier.citationJournal of Instrumentation (JINST). 2022, 17 (4), .en_US
dc.identifier.issn1748-0221
dc.identifier.urihttps://hdl.handle.net/11250/3057857
dc.description.abstractWith the combination of the highly granular pixel ASIC Timepix3 by the Medipix3 collaboration and several technologies we are developing a range of detectors. These technologies are bump bonded sensors, microchannel plates (MCP) and photolithographically postprocessed gas amplification stages (InGrid). For example, we are using the combination of the ASIC and an InGrid for the development of X-ray detectors for X-ray polarimetry and for axion search at IAXO. Based on the combination of the ASIC and silicon sensors we are developing a tracker or respectively a beam telescope. The combination of the ASIC and a microchannel plate will be used for neutron detectors. As this range of detectors has several requirements towards the readout and control system and a wide range of designs from low- to high-rate (Hz to MHz) and from single- to multichip, a versatile readout system is needed which adapts these applications without producing too much overhead for the others. To fulfil these requirements, we are developing a modular and scalable readout and control system based on the basil framework — a modular data acquisition system and system testing framework. The fully open-source implementation uses Verilog for the firmware and Python for the software. The system supports several FPGA boards to offer different applications a range of capabilities. One of these FPGA boards is the Scalable Readout System (SRS) by RD51 which offers scalability in low to medium rate applications. For high-rate applications we are working towards the firmware implementation on Xilinx adaptive compute acceleration platform. Besides the scalability, the system offers an optional monitoring interface via a microcontroller for monitoring chip temperatures and power supply voltages. Additionally, further external sensors could be connected to the monitoring system for example via I2C or SPI. For controlling the full system, the software offers a command line interface and a graphical user interface. Both interfaces also include an online event display to monitor the raw data. Additional meta data and data of the monitoring system is stored in a database and can be visualised with a monitoring dashboard.en_US
dc.language.isoengen_US
dc.publisherIOP Publishingen_US
dc.titleSRS-based Timepix3 readout systemen_US
dc.title.alternativeSRS-based Timepix3 readout systemen_US
dc.typePeer revieweden_US
dc.typeJournal articleen_US
dc.description.versionpublishedVersionen_US
dc.rights.holderThis version will not be available due to the publisher's copyright.en_US
dc.source.pagenumber0en_US
dc.source.volume17en_US
dc.source.journalJournal of Instrumentation (JINST)en_US
dc.source.issue4en_US
dc.identifier.doi10.1088/1748-0221/17/04/C04015
dc.identifier.cristin2024655
cristin.ispublishedtrue
cristin.fulltextoriginal
cristin.qualitycode1


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