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dc.contributor.authorLagraviere, Jeremie Alexandre Emilien
dc.contributor.authorLangguth, Johannes
dc.contributor.authorSourouri, Mohammed
dc.contributor.authorHa, Hoai Phuong
dc.contributor.authorCai, Xing
dc.date.accessioned2017-03-13T08:37:16Z
dc.date.available2017-03-13T08:37:16Z
dc.date.created2016-09-26T18:27:00Z
dc.date.issued2016
dc.identifier.isbn978-1-5090-2088-1
dc.identifier.urihttp://hdl.handle.net/11250/2433866
dc.description.abstractUsing large-scale multicore systems to get the maximum performance and energy efficiency with manageable programmability is a major challenge. The partitioned global address space (PGAS) programming model enhances programmability by providing a global address space over large-scale computing systems. However, so far the performance and energy efficiency of the PGAS model on multicore-based parallel architectures have not been investigated thoroughly. In this paper we use a set of selected kernels from the well-known NAS Parallel Benchmarks to evaluate the performance and energy efficiency of the UPC programming language, which is a widely used implementation of the PGAS model. In addition, the MPI and OpenMP versions of the same parallel kernels are used for comparison with their UPC counterparts. The investigated hardware platforms are based on multicore CPUs, both within a single 16-core node and across multiple nodes involving up to 1024 physical cores. On the multi-node platform we used the hardware measurement solution called High definition Energy Efficiency Monitoring tool in order to measure energy. On the single-node system we used the hybrid measurement solution to make an effort into understanding the observed performance differences, we use the Intel Performance Counter Monitor to quantify in detail the communication time, cache hit/miss ratio and memory usage. Our experiments show that UPC is competitive with OpenMP and MPI on single and multiple nodes, with respect to both the performance and energy efficiency.nb_NO
dc.language.isoengnb_NO
dc.publisherIEEEnb_NO
dc.relation.ispartofProceedings of the 14th IEEE International Conference on High Performance Computing & Simulation (HPCS 2016)
dc.titleOn the performance and energy efficiency of the PGAS programming model on multicore architecturesnb_NO
dc.typeChapternb_NO
dc.typeConference objectnb_NO
dc.typePeer reviewednb_NO
dc.source.pagenumber800-807nb_NO
dc.identifier.doi10.1109/HPCSim.2016.7568416
dc.identifier.cristin1385871
dc.description.localcodeThis is the authors' accepted and refereed manuscript to the article. © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.nb_NO
cristin.unitcode194,63,35,0
cristin.unitnameInstitutt for elektronikk og telekommunikasjon
cristin.ispublishedtrue
cristin.fulltextpostprint
cristin.qualitycode1


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