Blar i Fakultet for informasjonsteknologi og elektroteknikk (IE) på tidsskrift "Design, Automation and Test in Europe (DATE)"
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FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
(Journal article; Peer reviewed, 2019)The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing ...