• A Systematic Approach to Automated Construction of Power Emulation Models 

      Bjørnseth, Benjamin Andreassen; Djupdal, Asbjørn; Natvig, Lasse (Chapter, 2016)
      Efficient estimation of power consumption is vital when designing large digital systems. The technique called power emulation can speed up estimation by implementing power models alongside a design on an FPGA. Current ...
    • A vectorized k-means algorithm for compressed datasets: design and experimental analysis 

      Al Hasib, Abdullah; Cebrian, Juan Manuel; Natvig, Lasse (Journal article; Peer reviewed, 2018)
      Clustering algorithms (i.e., Gaussian mixture models, k-means) tackle the problem of grouping a set of elements in such a way that elements from the same group (or cluster) have more similar properties to each other than ...
    • Accelerating the Regina Network Flow Simulator on Multi-core Systems 

      Eleyat, Mujahed (Doctoral Theses at NTNU, 1503-8181; 262, Doctoral thesis, 2014)
      Emerging multi-core processors, which came as a result of manufacturers inability to keep increasing the frequency of single core processors, represent a great but also challenging opportunity to accelerate compute-intensive ...
    • Acceleration with OmpSs and Neon/OpenCL on ARM Processor 

      Lillesand, Trond Inge (Master thesis, 2013)
      In this thesis, the application kernels 2D-Convolution and Merge Sort are implemented in OmpSs, NEON and OpenCL on an Arndale development board containing an Exynos 5 SoC. The SoC contains an ARM Cortex A15 dual processor ...
    • Bandwidth-Aware Prefetching in Chip Multiprocessors 

      Grannæs, Marius (Master thesis, 2006)
      Chip Multiprocessors (CMP) are an increasingly popular architecture and increasing numbers of vendors are now offering CMP solutions. The shift to CMP architectures from uniprocessors is driven by the increasing complexity ...
    • BSPlab - experiment manager (BEM) 

      Klepaker, Erlend Søreide (Master thesis, 2006)
      Dette dokumentet beskriver utviklingen av en grafisk eksperimentomgivelse for BSPlab. BSPlab er en parallell datamaskinsimulator, som gjør det mulig å simulere kjøringer av programmer skrevet for BSP-modellen (Bulk Synchronous ...
    • BSPlab - experiment manager (BEM) 

      Klepaker, Erlend Søreide (Master thesis, 2006)
      Dette dokumentet beskriver utviklingen av en grafisk eksperimentomgivelse for BSPlab. BSPlab er en parallell datamaskinsimulator, som gjør det mulig å simulere kjøringer av programmer skrevet for BSP-modellen (Bulk Synchronous ...
    • BSPlab til folket 

      Lundereng, Torje; Østby, Erik (Master thesis, 2005)
      Dette dokumentet beskriver flyttingen av BSPlab fra Microsoft Visual Studio-utviklingsplattformen til GCC på Linux og MinGW på Windows. BSPlab er et simuleringsverktøy som gjør det mulig å simulere BSP-programmer på en ...
    • Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications 

      Iordan, Alexandru Ciprian; Jahre, Magnus; Natvig, Lasse (Journal article; Peer reviewed, 2013)
      Cycle-accurate simulation is an important tool that depends on the computational power of supercomputers. Unfortunately, simulations of modern multi-core platforms can take weeks or months. In this paper, we look into the ...
    • Climbing Mont Blanc - A Prototype System for Online Energy Efficiency Based Programming Competitions on ARM Platforms 

      Støa, Simen; Follan, Torbjørn (Master thesis, 2015)
      The Climbing Mont Blanc (CMB) system is an online judge with emphasis on energy-efficiency. In this thesis, the existing prototype of the system has been further developed and improved. Continual user testing was conducted ...
    • Climbing Mont Blanc - Back-end Improvements 

      Ingebrigtsen, Fredrik Pe (Master thesis, 2017)
      Energy efficiency in computing is becoming more and more important. With the rise of smart phones, a whole new industry was born where having a more energy efficient system would mean longer battery life and an edge over ...
    • Climbing Mont Blanc and Scalability 

      Chavez, Christian (Master thesis, 2016)
      This thesis details a proposed system implementation upgrade for the CMB system, accessible at \url{climb.idi.ntnu.no}, which profiles C/C++ code for its energy efficiency on an Odroid-XU3 board, which utilises a Samsung ...
    • Computer game based learning - SimComp 

      Friis, Nicolai (Master thesis, 2005)
      This report is the result of a computer architecture simulation game development project. The goals of the project were to develop conceptual ideas for a game that could be used in teaching computer architecture at a ...
    • Efficient multicore programming for industrial applications 

      Sørli, Ole Martin; Tøndel, Magne (Master thesis, 2010)
      Software and hardware developers of today are leaning more and more towards the use of multicore environments. For well over 30 years, since the early 1970 s, the evolution of processor performance has been centered ...
    • Enabling Research on Energy-Efficient System Software Using the SHMAC Infrastructure 

      Bjørnseth, Benjamin (Master thesis, 2015)
      The energy efficiency of computer systems is becoming an increasingly important constraint in the design of microprocessors. Energy consumption impacts battery life and electricity bills, while power consumption is ...
    • Energy Aware RTOS for EFM32 

      Spalluto, Angelo (Master thesis, 2011)
      Power consumption is a major concern for portable or battery-operated devices.Recently, new low power consumption techniques have been used to achieveacceptable autonomy battery-powered systems. FreeRTOS is a real-time ...
    • Energy Efficiency and Performance Evaluation of Register Level Bitonic Sort: on ARM Mali Powered Exynos 5 Processor 

      Guise, Matthew (Master thesis, 2014)
      Energy is one of the most important aspects impacting the reality of reach-ing exascale computing capabilities. In order to build super computers withthis computing power new hardware needs to be considered in their de-sign. ...
    • Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study 

      Al Hasib, Abdullah; Natvig, Lasse; Kjeldsberg, Per Gunnar; Cebrian, Juan Manuel (Journal article; Peer reviewed, 2017)
      Thread-level and data-level parallel architectures have become the design of choice in many of today’s energy-efficient computing systems. However, these architectures put substantially higher requirements on the memory ...
    • Energy Efficiency Experiments on Samsung Exynos 5 Heterogeneous Multicore using OmpSs Task Based Programming 

      Holmgren, Rune (Master thesis, 2015)
      This thesis explore the energy efficiency of task based programming with OpenMP SuperScalar (OmpSs) on the heterogeneous Samsung Exynos 5422 system on a chip. The system features small energy efficient cores, large high ...
    • Energy Efficiency Studies of Mont Blanc Applications 

      Holden, Mads (Master thesis, 2013)
      In this thesis, the performance and energy efficiency of four different implementations of matrix multiplication, written in OmpSs and OpenCL, is tested and evaluated. The benchmarking is done using an Intel Ivy Bridge ...