• Energy Efficient Computing on Multi-core Processors: Vectorization and Compression Techniques 

      Al Hasib, Abdullah (Doctoral theses at NTNU;2018:143, Doctoral thesis, 2018)
      Over the past few years, energy consumption has become the main limiting factor for computing in general. This has led CPU vendors to aggressively promote parallel computing using multiple cores without significantly ...
    • Energy Efficient Task Pool Scheduler in OmpSs 

      Martinsen, Thomas Bølstad (Master thesis, 2013)
      The European Mont-Blanc project aims to build future exascale systems using energy efficient low-power devices. Exascale systems built using low-power devices will require a large number of processors to achieve competitive ...
    • Evaluering av Chip Multiprosessor Simulatorer 

      Lande, Arnt Jørgen (Master thesis, 2006)
      This thesis presents some of the simulators that are available for simulation of computer architectures, with a special emphasis on simulating chip multiprocessor (CMP) architectures. The simulators Rsim, Asim, SimOS, ...
    • Experiments towards digital exam with auto-grading in C++ programming courses 

      Mathisen, Thea Christine; Lier, Johannes Omberg (Master thesis, 2016)
      Climbing Mont Blanc (CMB) is an online judge system especially suited for evaluating energy efficient programming solutions currently in development by a team of professors and master students at the Norwegian University ...
    • Funksjonsbuffer i maskinvare 

      Fredriksen, Tord Andreas (Master thesis, 2005)
      Rekonfigurerbar maskinvare har i den siste tiden vist seg å være et særdeles nyttig verktøy i forbindelse med akselerasjon av forskjellige algoritmer. Spesielt gjelder dette algoritmer som enkelt lar seg parallellisere. ...
    • GNU Debugger for Single-ISA Heterogeneous MAny-Core System (SHMAC) 

      Seime, Bjørn Christian (Master thesis, 2014)
      Processors have historically attained performance improvements primarily by increasing frequency and the number of transistors. As the transistor density increases, keeping the power density constant gets harder. As a ...
    • Identification of System Scenarios in Dynamic Embedded Systems 

      Hammari, Elena (Doctoral theses at NTNU;2018:242, Doctoral thesis, 2018)
      Modern embedded systems are characterized by complex functionality and run-time adaptivity to their environment. The embedded software has grown in size and become more data-dependent. Its resource needs are changing ...
    • Implementation and testing of shadow tags in the M5 simulator 

      Vinsnesbakk, Sigmund (Master thesis, 2008)
      The performance gap between CPU and main memory is a limiting factor for the performance in computers. Caches are used to bridge this gap. Caches give higher performance if the correct blocks are in place when the CPU needs ...
    • Implementation of Floating-point Coprocessor 

      Skogstrøm, Kristian (Master thesis, 2005)
      This thesis presents the architecture and implementation of a high-performance floating-point coprocessor for Atmel's new microcontroller. The coprocessor architecture is based on a fused multiply-add pipeline developed ...
    • Improving System Usability of Climbing Mont Blanc - An Online Judge for Energy Efficient Programming 

      Magnussen, Sindre (Master thesis, 2016)
      For each release of a new smartphone model, the limits of their CPUs, so called heterogeneous multicore processors, are pushed. As a result, the usage of such processors has gained an increased interest outside the mobile ...
    • Improving the Energy-Efficiency of Task Based Programming on Chip Multiprocessors 

      Iordan, Alexandru Ciprian (Doctoral theses at NTNU, 2017:175, Doctoral thesis, 2017)
      In the early 2000s, the superscalar CPU paradigm reached the point of diminishing returns mainly due to power requirements and overheating concerns. Faced with a constant demand for performance, hardware developers were ...
    • Improving the Performance of Parallel Applications in Chip Multiprocessors with Architectural Techniques 

      Jahre, Magnus (Master thesis, 2007)
      Chip Multiprocessors (CMPs) or multi-core architectures are a new class of processor architectures. Here, multiple processing cores are placed on the same physical chip. To reach the performance potential of these architectures ...
    • Improving the Performance of Processor Core Simulation in the M5 Simulator 

      Bertheussen, Håkon (Master thesis, 2008)
      Simulators are often used to evaluate new ideas in computer architecture research. Unfortunately, detailed simulation is computationally expensive, leading to long simulation turn-around times. This is particularly true ...
    • Increasing SpMV Energy Efficiency Through Compression: A study of how format, input and platform properties affect the energy efficiency of Compressed Sparse eXtended 

      Simonsen, Lars-Ivar H (Master thesis, 2013)
      This work is a continuation and augmentation of previous energy studies ofCompressed Sparse eXtended (CSX), a framework for efficiently executing SparseMatrix-Vector Multiplication (SpMV).CSX was developed by the CSLab at ...
    • Java Virtual Machine - Memory-Constrained Copying: Part 1: Main report 

      Amundsen, Kai Kristian (Master thesis, 2005)
      Atmel is inventing a new microcontroller that is capable of running Java pro- grams through an implementation of the Java Virtual Machine. Compared to industry standard PCs the microcontroller has limited processing power ...
    • Linear Programming on the Cell/BE 

      Eldhuset, Åsmund (Master thesis, 2009)
      Linear programming is a form of mathematical optimisation in which one seeks to optimise a linear function subject to linear constraints on the variables. It is a very versatile tool that has many important applications, ...
    • Linux for SHMAC 

      Amundsen, Håkon Furre; Andersson, Joakim Erik Christopher (Master thesis, 2014)
      For several years it has been possible to improve processor performance by taking advantage of the ever increasing transistor density.Recently, the power demand of processors has exceeded their power budget, so it is no ...
    • Multi-core programming with OpenCL: performance and portability: OpenCL in a memory bound scenario 

      Fagerlund, Olav Aanes (Master thesis, 2010)
      With the advent of multi-core processors desktop computers have become multiprocessors requiring parallel programming to be utilized efficiently. Efficient and portable parallel programming of future multi-core processors ...
    • NanoRisc 

      Rand, Peder (Master thesis, 2005)
      This report gives a short introduction of the Norwegian wireless electronics company Chipcon AS, and goes on to account for the state of the art of small IP processor cores. It then describes the NanoRisc, a powerful ...
    • NanoRisc C-compiler 

      Bakke, Dagfinn (Master thesis, 2006)
      This masters thesis report presents the work leading to a C compiler for the NanoRisc processor. The NanoRisc is a general purpose embedded RISC-processor with simple architecture aimed at replacing custom logic in Systems ...