Browsing NTNU Open by Author "Svarstad, Kjetil"
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3D Perspective Video Scaling Effects on FPGA
Karlsen, Eivind (Master thesis, 2013)The goal of this thesis was to design a video scaler able to do a perspective transform on a video stream. The scaler should be designed in VHDL and for FPGA, and the implementation should focus on achieving a low area ... -
A Pragmatic Approach to Modulation Scaling Based Power Saving for Maximum Communication Path Lifetime in Wireless Sensor Networks
Malavia Marín, Raúl (Master thesis, 2008)The interest in Wireless Sensor Networks is rapidly increasing due to their interesting advantages related to cost, coverage and network deployment. They are present in civil applications and in most scenarios depend upon ... -
A programmable DSP for low-power, low-complexity baseband processing
Næss, Hallvard (Master thesis, 2006)Software defined radio (SDR) is an emerging trend of radio technology. The idea is basically to move software as close to the antenna of a radio system as possible, to improve flexibility, adaptability and time-to-market. ... -
Adaptive Store and Forward - A look into possible solutions for the increasing resource consumption in wireless sensor networks
Homb, Gunnar Ranøyen (Master thesis, 2016)Over the recent years the interest for wireless sensor networks and Internet of Things (IoT) has grown significantly. As a consequence of this, there is a need for solutions to conserve restricted resources such as energy ... -
Aksellerering av nevrale nettverk for søkeordsdeteksjon på FPGA ved hjelp av Intel OpenVINO og Xilinx DNNDK
Nilsen, Anders (Master thesis, 2019)Nevrale nettverk brukes i nesten alle enheter med talegjenkjenning, som blant annet Alexa fra Amazon og Siri fra Apple. Disse nettverkene må kunne klassifisere store ordforråd med så liten forsinkelse som mulig. Dette ... -
An adaptive high-throughput edge detection filtering system using dynamic partial reconfiguration
Orlandic, Milica; Svarstad, Kjetil (Journal article; Peer reviewed, 2018)This paper proposes an architecture consisting of various edge detection filters implemented on modern FPGA platforms exploiting a feature of dynamic partial reconfiguration (DPR). The developed system targets small-scale ... -
An Area Efficient Hardware Architecture Design for H.264/AVC Intra Prediction Reconstruction Path based on Partial Reconfiguration
Orlandic, Milica; Svarstad, Kjetil (Chapter, 2013)The H.264/AVC standard supports intra prediction in order to reduce spatial redundancy in the video frame. The intra prediction process for one macro block requires reconstructing the left and top neighbor macro blocks ... -
Analyse, dekomponering og rekonstruksjon av FPGA-konfigurasjoner for AHEAD: Ambient Hardware, Embedded Architectures on Demand
Hauge, Ingar (Master thesis, 2006)Utvikling av maskinvare for (re)programmerbar mikroelektronikk har tradisjonelt vært basert på bruk av proprietære DAK-verktøy på alle abstraksjonsnivå. Den tradisjonelle designflyten forutsetter at alle utviklingsaktivitetene ... -
Applicability of the Residue Number System in a Radio Receive Chain
Fylkesnes, Eivind (Master thesis, 2016)This thesis explores the residue number system and how it can be used in a radio receiver. In this number system the numbers are divided up into several residues. Each of these residues is associated with one particular ... -
Applying a Digital Verification Approach to an Analog Protocol - Further development of a reusable verification component based on the Universal Verification Methodology
Ramstad-Evensen, Christoffer (Master thesis, 2016)Analog and mixed-signal circuit designs are more important now than ever, due to the popularity of wearable and wireless electronic devices. The forecast of the Internet of Things (IoT) suggest that the need for advanced ... -
Arkitektur-beskrivelse for AHEAD
Refnin, Lars Olav (Master thesis, 2006)Rapporten er skrevet fordi AHEAD prosjektet ser behovet for et ADL til automatisk plassering av HW moduler og SW moduler innad på en FPGA. AHEAD er en videretuvikling av Amibesense, men inneholder ingen generell prosessor, ... -
Audio decompression software for handheld devices
Nilsen, Andreas Danner (Master thesis, 2006)Falanx Microsystems have developed a set of hardware IP cores for graphic acceleration on small, handheld devices. But, a programmable Graphics Processing Unit (GPU) can be used for more than just graphics, and this may ... -
Automated verification flow using Jenkins build server
Parra Diaz, Juan Camilo (Master thesis, 2016)This assignment is a continuation of the project of fall 2015, where a linked approach for automation of coverage extraction information was implemented using questa Sim. Therefore the current Master Thesis project focuses ... -
Automatic Dynamic Clock Gate Analysis
Aune, Amund (Master thesis, 2018)The clock gate is a logic cell seen in most modern electronic integrated circuits. The clock gate is used to stop a clock signal from propagating through the circuit, and hence minimize dynamic power consumption. Clock ... -
Compiling Regular Expressions into Non-Deterministic State Machines for Simulation in SystemC
Volden, Kjetil (Master thesis, 2011)With Moore s law exponentially increasing the number of transistors on inte-grated circuits, developers fail to keep up. This makes chip area an increasinglycheap resource. At the same time, researchers and developers are ... -
Computation of prime cubes of a complex boolean function based on BDDs - continuation on probability of time unfolded prime cubes
Vestli, Snorre Nilssen (Master thesis, 2013)With decreasing feature size and increasing complexity of integrated circuits, effective tools for verification and testing are in high demand. When testing large and complex state machines, effective tools for calculating ... -
Construction of digital integer arithmetic: FPGA implementation of high throughput pipelined division circuit
Øvergaard, Johan Arthur (Master thesis, 2009)This assignment has been given by Defence Communication (DC) which is a division of Kongsberg Defence and Aerospace(KDA). KDA develops amongst other things military radio equipment for communication and data transfer. In ... -
Conversion of a simple Processor to asynchronous Logic
Vee, Bjørn Thomas Søreng (Master thesis, 2014)This paper discuss the conversion of a simple 16-bit synchronous RISC based processor into asynchronous logic. The most important targets were the simplicity of the conversion, to see how the tools reacted to asynchronous ... -
Deep Learning Based FPGA-CPU Acceleration
Jalabert, Rodolfo (Master thesis, 2019)Formålet med dette prosjektet er å fortsette å utforske nye måter å akselerere sequentialcomputer kode, og finne ut om maskinens læringsteknikker tilgjengelig i dag er i stand til å hjelpe oss med denne oppgaven. Kjerneideen ... -
Design and analysis of a video scaler suited for FPGA implementation
Tysse, Tom Erik (Master thesis, 2017)A video scaler, is a module that receives a picture, enlarge or shrink it, and sends it back.The video scaler in this thesis was made to be part of an AXI-Stream Video System thatis suited to be implemented on a FPGA.The ...