Blar i NTNU Open på forfatter "Själander, Magnus"
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Implementing Data Cache Access Memoization (DCAM) in hardware to measure L1 DC and DTLB energy efficiency
Vedvik, Edgar (Master thesis, 2019)Nivå-1 data-hurtiglager (L1 DC) og mellomlager for dataoversetting (DTLB) er essensielle i nåtidens minnehierarki for å gi raskere tilgang til data og redusere antall ventesykluser. Disse strukturene bli aksessert ofte, ... -
Implementing RVSDG as a dialect of MLIR
Bjørstad, Halvor (Master thesis, 2023)Slutten på Dennard-skaleringen og det påfølgende skiftet til flerkjernede og heterogene prosessorarkitekturer har flyttet ansvaret for å øke ytelsen til programvare over på programmerere og verktøyene deres. Et behov for ... -
Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing
Sasnayake Mudiyanselage, Lahiru Kasun Rasnayake; Själander, Magnus (Chapter, 2019)Low-precision matrix multiplication has gained significant interest in the research community due to its applicability in the quantized neural network domain. As a result, a multitude of variable precision hardware designs ... -
Improving Memory Scheduling of an Out-of-Order Core
Young, Marcus Stensby (Master thesis, 2023)Dette prosjektet har som mål å optimalisere minnesystemet til RISC-V Berkeley Out-of-Order Machine (BOOM) prosessorkjernen ved å forbedre håndteringen av instruksjoner som bommer i L1 cachen i Load-Store enheten (LSU). Før ... -
Improving System Usability of Climbing Mont Blanc - An Online Judge for Energy Efficient Programming
Magnussen, Sindre (Master thesis, 2016)For each release of a new smartphone model, the limits of their CPUs, so called heterogeneous multicore processors, are pushed. As a result, the usage of such processors has gained an increased interest outside the mobile ... -
Investigating Speculative Side-Channel Protection
Lauvdal, John Askeland (Master thesis, 2023)Spekulasjon er en mye brukt optimalisering i prosessor kjerner og har bidratt til å forbedre ytelsen ved å utføre mer arbeid og forhindre at pipelinen står stille og venter. Det er imidlertid i senere tid blitt oppdaget ... -
Investigating the Usefulness of Simulators and Prototypes as Research Tools
Kvalsvik, Amund Bergland (Master thesis, 2021)Økende kompleksitet i prosessordesign har gjennom årene gjort forskning innenfor datamaskinarkitektur mer komplisert. For å forenkle forskningsprosessen har mange forskere begynt å bruke simulatorer som gem5, som muliggjør ... -
Modelling Inclusive Cache Hierarchies in Multi-core Systems
Gaustad, Anders (Master thesis, 2022)Ytelsen til moderne datasystemer er ofte begrenset av hastigheten til minnet da hastigheten til prosessorer har økt mye mer enn hastigheten til minnesystemer over flere år. Dette har ført til at minnesystemer ofte blir en ... -
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing
Umuroglu, Yaman; Davide, Conficconi; Rasnayake, Lahiru; Preusser, Thomas B.; Själander, Magnus (Peer reviewed; Journal article, 2019)Matrix-matrix multiplication is a key computational kernel for numerous applications in science and engineering, with ample parallelism and data locality that lends itself well to high-performance implementations. Many ... -
Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization
Chakraborty, Shounak; Saha, Sangeet; Själander, Magnus; McDonald-Maier, Klaus (Peer reviewed; Journal article, 2021)Achieving high result-accuracy in approximate computing (AC) based real-time applications without violating power constraints of the underlying hardware is a challenging problem. Execution of such AC real-time tasks can ... -
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions
Aimoniotis, Pavlos; Sakalis, Christos; Själander, Magnus; Kaxiras, Stefanos (Peer reviewed; Journal article, 2021)Speculative side-channel attacks access sensitive data and use transmitters to leak the data during wrong-path execution. Various defenses have been proposed to prevent such information leakage. However, not all speculatively ... -
RVSDG: An intermediate representation for optimizing compilers
Reissmann, Nico; Meyer, Jan Christian; Bahmann, Helge; Själander, Magnus (Peer reviewed; Journal article, 2020)Intermediate Representations (IRs) are central to optimizing compilers as the way the program is represented may enhance or limit analyses and transformations. Suitable IRs focus on exposing the most relevant information ... -
Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference
Sakalis, Christos; Själander, Magnus; Kaxiras, Stefanos (Chapter, 2021)Speculative side-channel attacks consist of two parts: The speculative instructions that abuse speculative execution to gain illegal access to sensitive data and the side-channel instructions that leak the sensitive data. ... -
Static Instruction Scheduling for High Performance on Limited Hardware
Tran, Kim-anh; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Spiliopoulos, Vasileios; Kaxiras, Stefanos; Jimborean, Alexandra (Journal article; Peer reviewed, 2017)Complex out-of-order (OoO) processors have been designed to overcome the restrictions of outstanding long-latency misses at the cost of increased energy consumption. Simple, limited OoO processors are a compromise in terms ... -
Strict Memory Protection for Microcontrollers
Sveen, Erlend (Master thesis, 2019)Moderne datasystemer beskytter prosesser fra hverandre med minnebeskyttelse. Mikrokontrollersystemer, som mangler støtte for minnevirtualisering, bruker typisk sett kun minnebeskyttelse for områder som programmereren finner ... -
SWOOP: Software-Hardware Co-design for Non-speculative, Execute-Ahead, In-Order Cores
Tran, Kim-anh; Jimborean, Alexandra; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Kaxiras, Stefanos (Chapter, 2018)Increasing demands for energy efficiency constrain emerging hardware. These new hardware trends challenge the established assumptions in code generation and force us to rethink existing software optimization techniques. ... -
Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services
Nishtala, Rajiv; Petrucci, Vinicius; Carpenter, Paul; Själander, Magnus (Peer reviewed; Journal article, 2020)Many of the important services running on data centres are latency-critical, time-varying, and demand strict user satisfaction. Stringent tail-latency targets for colocated services and increasing system complexity make ... -
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution
Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Jimborean, Alexandra; Själander, Magnus (Peer reviewed; Journal article, 2020)Since the introduction of Meltdown and Spectre, the research community has been tirelessly working on speculative side-channel attacks and on how to shield computer systems from them. To ensure that a system is protected ... -
WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption
Chakraborty, Shounak; Själander, Magnus (Peer reviewed; Journal article, 2021)Managing thermal imbalance in contemporary chip multi-processors (CMPs) is crucial in assuring functional correctness of modern mobile as well as server systems. Localized regions with high activity, e.g., register files, ... -
Way-predictive instruction cache access in Rocket Chip processor with RISC-V ISA
Akhunov, Khakim (Master thesis, 2020)Ytelsen til sentrale prosesseringsenheter er begrenset i energiforbruk i disse dager. Mer effektive prosessorer er nødvendige for å muliggjøre forbedret ytelse. Moderne datasystemer utnytter komplekse prosessorer som ...