SystemVerilog real number modeling (SV-RNM) allows the behavior modeling of analog components in the digital solver environment.
The simulation time of SV-RNM can be comparable with that of conventional digital simulation.
SV-RNM therefore can be a useful tool to verify the functionality of a System-on-Chip (SoC) at top level, as its run time can be significantly lower than the more accurate tools such as SPICE.
This can also help reduce the required man-hour and therefore the cost of verification.
This project implements behavior model of analog components such as LDO and decoupling capacitor using SV-RNM.
In order to compare with a more realistic system, a mixed-signal SoC is generated using open source tools. In particular, OpenLane which is a open-source tool to generate GDS from RTL is employed.
This requires generating GDS for analog and digital components individually and integrating them for a top-level system into OpenLane.
Different modeling approaches are also considered for SV-RNM to investigate their effectiveness.
In the case of LDO, it is treated as a current source and its output current is implemented using (1) arctan function, (2) MOS transistor model and (3) MOS transistor model with a low pass filter.
These models contain parameters which can be configured. It is necessary to tune them to achieve a reasonable agreement with SPICE counterpart.
This can require the knowledge of the design of analog components for calibrating the SV-RNM models.
In the case of the decoupling capacitor, different numerical methods such as rectangle rule and trapezoid rule are considered.
In this case, the difference between different numerical methods for the decoupling capacitor appears to be negligible due to the presence of the large capacitance.
At a component level, SV-RNM can reduce the simulation time by a factor of 100 or more, compared with SPICE.
Individual components are integrated together to form the top-level mixed-signal SoC.
SPICE simulation of such a large system can be impractical.
Some modifications are necessary to reduce the size of the netlist but these can lead to loss of details.
Such necessities illuminate the challenge in simulating a large, mixed-signal system using more accurate tools and the need for a more efficient method.
SV-RNM is able to capture the behavior of the larger system adequately when compared with SPICE and it can speed up the simulation time by a factor of 10000 or more.
After the calibration to adequately capture the behavior of components, SV-RNM can achieve a significant reduction in simulation times. This allows to test the functionality of the chip under multiple scenarios.
Such a reduction in simulation times demonstrates that SV-RNM can be a valuable tool in effort to reduce the verification gap.
