| dc.description.abstract | In this thesis, An Application-Specific Integrated Circuit(ASIC) implementation of a 16-bit low-power Arithmetic Logic Unit(ALU) for Ultrasound CPU is proposed. The proposed ALU design can perform Addition and Multiplication as Arithmetic Operations and perform AND, OR, XOR as logic operations.
The RTL code and the testbench for the Proposed ALU are written in Verilog HDL, and the functional verification is done in the Mentor Questasim simulator. The gate-level synthesis is performed in Cadence Genus Synthesis Solution, and the Physical design is done with Cadence Innovus Implementation System. The Post-Synthesis and Post-Layout Simulation are accomplished in Mentor Questasim Tool.
The total power consumption is 523nW is, of which 27.5nw is leakage power, 137.4nW is switching power, and 358nW is internal power. The total number of gate count in terms of NAND gate is 1418, and the Area is 1454.184 sq-um(Unit Micron). 45nm CMOS technology is used to design the proposed ALU. The operating frequency is 10MHz, and the voltage is 0.9V. | |