Low Voltage Logic and Memories on Silicon

Abstract

Data centers, sensor nodes in the internet of things, and handheld devices are all systems that require energy efficiency and low power operation to reduce electricity cost, fit within power budgets of energy harvesters, avoid overheating or increase battery lifetime. These requirements can be achieved by lowering the supply voltage of their integrated circuits. The power consumption is reduced as the circuit supply voltage is lowered down towards and below the threshold voltage of the transistors; this comes at the cost of increased propagation delays. There exists an application-dependent sweet-spot for the supply voltage referred to as the minimum energy point, where the energy per operation of the circuit is at its lowest. Voltage scaling in integrated circuits requires considerations during the design phase. Even though down-scaling the supply voltage of integrated circuits is a popular and effective means of achieving these goals, the relative impact that process, voltage, and temperature variations have on the functionality of the circuits also tend to increase with decreasing supply voltage. For memory subsystems within low power and energy-efficient circuits, variations in strength ratios between transistors can lead to an inability to write, inability to read, or inability to hold logic values. In this work, promising synchronous edge-triggered memory elements have been identified for low voltage operation. A comparative study of 9 data flip-flop circuit architectures at a target supply voltage of 200 mV has been performed. In the study all nine memory cells were sized and laid out using the same approach, setup time, hold time, minimum functional supply voltage, propagation delay, functionality in Monte Carlo simulations, power consumption and energy per cycle have been simulated for each data flip-flop on netlists extracted from the layout. The study revealed that the two most promising memory elements were the Pass Gate and the PowerPC flip-flops. The first had the lowest energy consumption per cycle for operating frequencies below 500 kHz, and for supply voltages below 400 mV, the lowest transistor count and the smallest layout footprint, it was also functional at the lowest supply voltage of 65 mV. The second, the PowerPC flip-flop, had the best power delay product, 26% of that of the worst flip-flop. Compact near-threshold static random access memory cells have also been investigated. Many Low voltage SRAM cells have been reported in the literature. However, most of them deploy multiple extra transistors as write- and read- assists to the conventional 6 transistor SRAM cell. We bring the loadless 4 transistor cell down to the near-threshold voltage domain by adding a 2 transistor read buffer. The loadless nature of the 4 transistor core acts as a write assist while the 2 transistor read buffer acts as a read assist, ensuring read-ability and write-ability at a supply voltage of 350 mV in a 28 nm fully depleted silicon on insulator technology for a 6 T cell. High sigma simulation results on a 128 kb memory macro of the cell show that it performs on par with state of the art low voltage memory. Three variants of the macro were explored where the peripheral logic consisted of low threshold-voltage, high threshold-voltage devices, and high threshold voltage devices with up-scaled lengths. For the three variants at a supply voltage of 350 mV, the retention power consumption of the 128 kb system was found to range from 1.31 μW to 71.09 μW, the maximum operational frequency was found to lie within 1.87 MHz and 14.97 MHz while the read energy varied from 13.08 to 75.21 fJ/operation/bit. The minimum retention voltage of the loadless SRAM cell was found to be 230 mV in Monte Carlo simulations. A study has been performed where we balance pull-up and pull-down networks in ultra-low-voltage logic gates to maximize noise margins and create robust lowpower minority-3 and Boolean logic gates. To balance the drive strength of the complementary networks in the gates, design-phase gate-length biasing and runtime back-gate biasing was applied. These gates have been combined into ultralow voltage 16- and 32- bit adders, and measurements were made on a physical prototype. The improvement in energy per 1-bit addition for the 32-bit adder was 37% at a supply voltage of 300 mV compared to the best reported adder in the same technology. For the 16 bit adder, the improvement was 25% at a supply voltage of 250 mV. In addition, the 32-bit adder was shown to be functional down to 125 mV for all ten chip-samples and down to 80 mV by tuning the drive strength of the pull-up networks, with back-gate biasing. To interface ultra-low-voltage circuit blocks, subthreshold to superthreshold level shifters have been examined. By applying the principle of write assist circuitry in low voltage memory cells to low voltage level shifters, an ultra-low voltage level shifter was created. A physical prototype was implemented and manufactured in 130 nm bulk CMOS to demonstrate the principle. The assist circuit of the level shifter ensures a propagation delay of 21.08 ns, which results in an energy-efficient level shifter consuming 25.9 fJ per conversion when up-converting near-threshold input signals of 300 mV to regular supply voltage signals of 1.2V. Measurement results on ten samples show that the level shifter support up-conversion of logic signals with mean value down to 31.1 mV. By tuning the balance between the pullup and pull-down networks the mean value of the lower limit is decreased to 14.3 mV. Macro-level schemes have been considered to reduce the power consumption of already voltage scaled low voltage memories. Low voltage memory cells are typically asymmetric in nature, which leads to state-dependent pros and cons. We have introduced a scheme that dynamically exploits content-dependencies in asymmetric memory cells where words are conditionally flipped during write operations to reach the more beneficial state for storage. A capacitive logic decision circuit is created to perform the word-flip operation, and the system is exemplified with a 1 kb static random access memory macro of asymmetric low voltage memory cells that have a state-dependent leakage quotient of 23. The memory array and the scheme was implemented and manufactured in a 130 nm bulk process. Measurement results, on a physical prototype of the exemplified memory macro, with the scheme activated, show an improvement of 11.93% in retention power consumption when storing 128 words concatenated from random bits that are uniformly distributed. By applying voltage scaling on CMOS circuits, we have gained further insight into circuit architectures and schemes that ensures ressilient and robust operation while yielding energy efficiency and low power consumption. The results of this work are identifications of promising circuit architectures as well as the introduction of new schematics and approaches to the design of low voltage memories and logic cells.