A Power-Efficient Low-noise and High Swing CMOS Amplifier for Neural Recording Applications

Abstract

In this paper, a power efficient, low-noise and high swing capacitively-coupled amplifier (CCA) for neural recording applications is proposed. The use of current splitting technique and current scaling technique in a current mirror operational transconductance amplifier (CM-OTA) has lead to a very good trade-off between power and noise. The presented architecture is simple, without cascode transistor while it has more than 80 dB open-loop gain without extra power consumption. As a result, the proposed strucuture has a better power efficiency factor (PEF) and output swing in comparison with previous reported architectures is increased to the 2Vov below the maximum supply voltage. In order to reduce flicker noise and achieve better trade-off between the power and noise, PMOS transistors with an optimum size have been utilized which operate in sub-threshold region. The amplifier is designed and simulated in a commercially available 0.18 µm CMOS technology. Monte Carlo simulations for process and mismatch have been carried out. The gain of the proposed amplifier is 39.22 dB in its bandwidth (3 Hz - 5 kHz). Total input-referred noise is 3.03 µVrms over 1 Hz - 10 kHz. The power consumption of the amplifier is 2.98 µW at supply voltage of 1.4 V. The noise efficiency factor (NEF) and PEF are 2.4 and 8.06, respectively. The output swing is about 1.16 V. It means the proposed amplifier can tolerate up to 13.2 mV peakto-peak input signal while its total harmonic distortion (THD) is less than 1%.