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dc.contributor.advisorAunet, Snorre
dc.contributor.advisorYtterdal, Trond
dc.contributor.authorVatanjou, Ali Asghar
dc.date.accessioned2020-02-24T13:11:17Z
dc.date.available2020-02-24T13:11:17Z
dc.date.issued2019
dc.identifier.isbn978-82-326-4323-3
dc.identifier.issn1503-8181
dc.identifier.urihttp://hdl.handle.net/11250/2643465
dc.description.abstractIn the present day microelectronics, supply voltage scaling has received an intense attention as an efficient approach to reduce the power consumption in battery-operated and energy-harvested wireless systems. However, process, voltage and temperature (PVT) variations increase with lowering the supply voltage. This poses a challenge to ultra-low voltage (ULV) design to make robust circuits while maintaining the energy efficiency. In this dissertation, ultra-low voltage building blocks are developed in 65 nm Bulk CMOS and 28 nm FDSOI technologies. The work focuses on making an optimal trade-off between the energy efficiency and the robustness of the building-blocks. At device level, combinations of higher order effects were considered. Static CMOS logic was used throughout the logic cells development. A constant effort was made to balance the drive strengths of the pull-up and pull-down networks with less area overhead and increase the functional yield of the cells. For the sequential elements, a single-phase clocked and contention free flip-flop structure was used. Measurement results confirmed robustness and energy efficiency of the circuits both in the 65 nm Bulk and 28 nm FDSOI technologies. In 65 nm, the obtained 119 mV and 84 mV minimum supply voltages for the Ripple Carry Adders (RCA) proved the robustness of two types of logic cells with thick and thin Gate-Oxide thicknesses. The functionality of the singlephase clocked D type flip-flops were proven down to 132 mV in a divide-by-3 circuit. In 28 nm FDSOI, a minimum functional supply voltage of 110 mV was achieved for RCAs and 8-bit multiplier based on Regular Threshold Voltage (RTV) devices. This is a demonstration of the functionality of both the combinational and sequential elements as the 8-bit multiplier contains the single-phased clocked flip-flops to sample outputs of the multiplier. Moreover, the minimum supply voltages of the 32-bit RCA samples reduced down to 80 mV by applying reverse back-gate voltages to the PMOS transistors. The 32-bit RCA based on minority-3 gates in 28 nm achieved an average energy per 1-bit addition of 0.65 fJ from the measurement results of nine samples. The average of measured energy per 1-bit addition of the 16-bit RCA was 0.77 fJ. From the measurements of ten samples, the implemented 8-bit multiplier in 28 nm obtained a minimum energy point of 47.2 fJ/cycle on average. The implemented logic cell library based on the Low Threshold Voltage (LVT) devices in 28 nm FDSOI was extended by adding specialized inverters for clock tree distribution and fixing the hold time violations. A simple approach for clock distribution is also presented when the sequential elements of the circuit are single-phase clocked and race free. A level-shifter capable of up-converting 39 mV to 1 V was implemented in 28 nm FDSOI. The diode connected devices were utilized to reduce the leakage current and decrease the minimum convertible input voltage levels. Moreover, the Single-NWELL (SNW) layout strategy was used along with the back-gate biasing and poly-biasing to create an adequate balance between the PMOS and NMOS drive strengths.
dc.language.isoengnb_NO
dc.publisherNTNUnb_NO
dc.relation.ispartofseriesDoctoral theses at NTNU;2019:362
dc.relation.haspartPaper 1: Bjerkedok, Jonathan Edvard; Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre. Modular Layout-friendly Cell Library Design Applied for Subthreshold CMOS. I: Proceedings of the 32nd Norchip Conference. IEEE conference proceedings 2014 https://doi.org/10.1109/NORCHIP.2014.7004747
dc.relation.haspartPaper 2: Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre. Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS. I: Proceedings of the 6th Asia Symposium on Quality Electronic Design. IEEE conference proceedings 2015 ISBN 978-1-4673-7495-8. s. 7-12 https://doi,org/10.1109/ACQED.2015.7273999
dc.relation.haspartPaper 3: Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre. Exploiting Short Channel Effects and Multi-Vt Technology for Increased Robustness and Reduced Energy Consumption, with Application to a 16-bit Subthreshold Adder Implemented in 65 nm CMOS. I: Proceedings, 2015 European Conference on Circuit Theory and Design. IEEE conference proceedings 2015 https://doi.org/ 10.1109/ECCTD.2015.7300053
dc.relation.haspartPaper 4: Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre. 4 Sub-/Near-Threshold Flip-Flops with Application to Frequency Dividers. I: Proceedings, 2015 European Conference on Circuit Theory and Design. IEEE conference proceedings 2015 https://doi.org/10.1109/ECCTD.2015.7300058
dc.relation.haspartPaper 5: Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre. 28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block. I: Proceedings of the 23rd International Conference - "Mixed Design of Integrated Circuits and Systems" (MIXDES), Lodz, Poland. IEEE conference proceedings 2016 https://doi.org/10.1109/MIXDES.2016.7529711
dc.relation.haspartPaper 6: Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre. Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28nm FDSOI. I: Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE conference proceedings 2015 https://doi.org/10.1109/NORCHIP.2015.7364372
dc.relation.haspartPaper 7: Vatanjou, Ali Asghar; Låte, Even; Ytterdal, Trond; Aunet, Snorre. Ultra-Low Voltage Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. IEEE Nordic Conference on Circuits and Systems https://doi.org/10.1109/NORCHIP.2016.7792895
dc.relation.haspartPaper 8: Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre. Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocessors and microsystems 2017 ;Volum 48. s. 11-20 https://doi.org/10.1016/j.micpro.2016.07.016
dc.relation.haspartPaper 9: Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing Journal publication printed in Elsevier Microprocessors and Microsystems. Volume 56, Pages 92-100, February 2018. https://doi.org/10.1016/j.micpro.2017.11.002
dc.relation.haspartPaper 10: Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre. An Ultra-Low Voltage and Low-Energy Level Shifter in 28 nm UTBB-FDSOI. IEEE Transactions on Circuits and Systems - II - Express Briefs 2018 ;Volum 66.(6) s. 899-903 https://doi.org/10.1109/TCSII.2018.2871637
dc.titleUltra Low-Power/Low-Energy CMOS Mixed-Signal Building Blocksnb_NO
dc.typeDoctoral thesisnb_NO
dc.subject.nsiVDP::Technology: 500::Electrotechnical disciplines: 540nb_NO


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