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dc.contributor.authorKoraei, Mostafa
dc.contributor.authorFatemi, Omid
dc.contributor.authorJahre, Magnus
dc.date.accessioned2019-11-06T07:38:33Z
dc.date.available2019-11-06T07:38:33Z
dc.date.created2019-10-14T15:11:17Z
dc.date.issued2019
dc.identifier.issn1544-3566
dc.identifier.urihttp://hdl.handle.net/11250/2626772
dc.description.abstractIterative Stencil Loops (ISLs) are the key kernel within a range of compute-intensive applications. To accelerate ISLs with Field Programmable Gate Arrays, it is critical to exploit parallelism (1) among elements within the same iteration and (2) across loop iterations. We propose a novel ISL acceleration scheme called Direct Computation of Multiple Iterations (DCMI) that improves upon prior work by pre-computing the effective stencil coefficients after a number of iterations at design time—resulting in accelerators that use minimal on-chip memory and avoid redundant computation. This enables DCMI to improve throughput by up to 7.7× compared to the state-of-the-art cone-based architecture.nb_NO
dc.language.isoengnb_NO
dc.publisherAssociation for Computing Machinery (ACM)nb_NO
dc.titleDCMI: A Scalable Strategy for Accelerating Iterative Stencil Loops on FPGAsnb_NO
dc.typeJournal articlenb_NO
dc.typePeer reviewednb_NO
dc.description.versionpublishedVersionnb_NO
dc.source.volume16nb_NO
dc.source.journalACM Transactions on Architecture and Code Optimization (TACO)nb_NO
dc.source.issue4nb_NO
dc.identifier.doi10.1145/3352813
dc.identifier.cristin1736938
dc.relation.projectEC/H2020/688403nb_NO
dc.description.localcodeThis article will not be available due to copyright restrictions (c) 2019 by ACMnb_NO
cristin.unitcode194,63,10,0
cristin.unitnameInstitutt for datateknologi og informatikk
cristin.ispublishedtrue
cristin.fulltextpostprint
cristin.qualitycode2


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