Energy Efficient Floating Point Unit for the SHMAC Platform

Abstract

Floating-point operations are critical for many applications where heterogenous computing is gaining traction. Floating-point implementation can be power hungry, however. As such, this thesis presents the architecture and implementation of an energy efficiet IP-free floating-point unit (FPU) for the RISC-V based Sodor CPU tile on the \acf{SHMAC} platform, and shows that general purpose FPUs can be implemented efficiently and with simple complexity in modern \acp{FPGA}.

The implemented design, which has been named FPU32, achieved latencies of 6, 8, 30 and 31 cycles for its add, multiply, divide and square root floating-point arithmetics. A total number of 3455 LUTs was needed for deployment on a Xilinx Zynq XC7Z020 FPGA, and the design achieved a measured dynamic power consumption of 157.66 mW. The architecture has undergone the scrutiny of large testvectors in order to verify its functinality, and the FPU has shown itself to be fully IEEE-754R compliant.