| dc.description.abstract | A 64-modulus prescaler operating at 5.8 GHz has been designed in a 0.18 μm CMOS process. The prescaler uses a four-phase high-speed ÷4 circuit at the input, composed of two identical cascaded ÷2 circuits implemented in pseudo-NMOS. The high-speed divider is followed by a two-bits phase switching stage, which together with the input divider forms a ÷4/5/6/7 circuit. The phase switching stage is mostly implemented in complementary CMOS. After this follows four identical ÷2/3 cells with local feedback, also implemented in complementary CMOS.
Other architectural approaches are also described and tried out. An architecture based solely the ÷2/3 cells with local feedback is presented. The ÷2/3 cells were implemented and simulated, and worked up to 2.3 GHz. An alternative high-speed divider based on an inverter ring interrupted by transmission gates is also described. Simulations showed that a divider using pseudo-NMOS inverters and CMOS transmission gates operated well and
gave out four signals evenly spaced in phase at a input frequency of 4.8 GHz. | |
