Design and Implementation of a High Resolution, Discrete-Time Delta-Sigma ADC

Abstract

This thesis do a study on delta-sigma type A/D converters to find good trade-offs and optimize a design for high resolution conversion in embedded applications. The main objective is to define a state of the art high-resolution delta-sigma ADC with main feature such as approximate 16 bits resolution and above 10MHz conversion rate. A behavioral model was developed in the the feasibility study to derive a complete design specification for a third-order fully differential discrete∆Σmodulator. The specifications were used in this thesis to implement the modulator in transistor-level. The circuit is developed in a 0.18um CMOS process technology that employs a standard supply voltage of 1.8 V.The OTAs are designed using folded cascode topology. A wide swing current mirror is used to bias the transistors, and switched CMFB circuit is implemented to stabilize the common mode output of the OTAs. A methodology called gm/ID is used to find dimensions for the transistors of the OTAs by characterizing their performances. The 1-bitquantizer is implemented as a latched comparator with low hysteresis. A two-phase non-overlapping clock generator with delayed phases is designed in order to operate the discrete circuit. The simulations on each corner of the technology confirm that the modulator satisfies the specifications, even in the worst case. The nominal simulation with transient noise gives a SINAD equals to 98.23dB which corresponds to a resolution of 16.2 bits.The total static power dissipation is 87uW with a FoM of 0.20pJ/step