FPGA Implementation of Hyperspectral Anomaly Detection Algorithm
MetadataShow full item record
On-board processing of hyperspectral data in satellites is done to perform a wide variety of tasks. Field-Programmable Gate Arrays (FPGAs) are often used for such tasks due to their reconfigurability and efficiency, especially when dealing with applications requiring matrix computation. One of these applications is anomaly detection. Anomaly detection might be used to discover algae, oil spills, micro-plastics and other irregularities in ocean and coastal areas. This might help us understand more about the ocean and to monitor the effects of global warming and human pollution. The Adaptive Causal anomaly detector (ACAD) is an anomaly detector (AD) developed to solve some of the issues that well-known ADs, such as the Reed-Xiaoli (RX) algorithm, faces. ACAD utilizes inverse matrix computation as a part of the anomaly detection. Computing the inverse matrix is an intensive task. It is therefore important that the algorithm chosen for inverse matrix computation is parallellizable and efficient. The Gauss-Jordan elimination was chosen due to its parallel computation and simplicity. ACAD is causal, meaning that it relies on previously executed computations. This enables real-time processing and makes it suitable for hardware implementation. ACAD also builds a binary anomaly map, which is beneficial with regards to data transmission, as this will lower transmission time and thereby energy. In this thesis, a proposed implementation of the ACAD algorithm has been made, designed to be scalable for large hyperspectral images. A parallel memory structure consisting of Block RAM (BRAM)-arrays of size $P\_bands$ have been made. $P\_bands$ is the number of spectral bands of the input pixel data to the ACAD AD. The correlation and inverse modules proposed in this implementation have a large degree of parallelism, computing and updating up to two rows of the correlation and inverse matrix respectively, of size $P\_bands$ $\times$ $P\_bands$, per clock cycle. The design is to be implemented on a Zynq-7000 series System-on-Chip (SoC).