Multi-Processor System-on-Chip Architectures for Wireless Applications

Abstract

Radio chip solutions today use one of two common high-level system architectures. In the first architecture, a microcontroller runs the protocol stack and the application runs on a separate application controller. The second architecture is a System-on-Chip solution where the protocol stack and application runs on the same microcontroller. The main advantage of the first solution is that it provides isolation while the second solution may have a lower cost and better energy efficiency.An alternative architecture is a Multi-Processor System-on-Chip (MPSoC) which uses two separate but tightly coupled heterogeneous microcontrollers. Consequently, one microcontroller runs the wireless protocol stack while the other microcontroller runs the user s application. This architecture has the potential to achieve the best of both worlds if the performance of the microcontrollers is carefully tuned to their tasks. Using separate microcontrollers on-chip can also be beneficial when the application and the radio subsystem both have hard real-time requirements.The main task of this assignment is to study possible architectures for MPSoCs with heterogeneous embedded microcontrollers. The aim is to isolate the application from the protocol subsystem. Since system cost is an important constraint, the task is to find the lowest cost and lowest power architecture that has acceptable performance. If time permits, the architectures should be evaluated with communication protocols like ANT, Bluetooth low energy and Gazell.