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dc.contributor.advisorNatvig, Lassenb_NO
dc.contributor.advisorRenno, Eriknb_NO
dc.contributor.authorSkogstrøm, Kristiannb_NO
dc.date.accessioned2014-12-19T13:33:00Z
dc.date.available2014-12-19T13:33:00Z
dc.date.created2010-09-03nb_NO
dc.date.issued2005nb_NO
dc.identifier348069nb_NO
dc.identifierntnudaim:1007nb_NO
dc.identifier.urihttp://hdl.handle.net/11250/250932
dc.description.abstractThis thesis presents the architecture and implementation of a high-performance floating-point coprocessor for Atmel's new microcontroller. The coprocessor architecture is based on a fused multiply-add pipeline developed in the specialization project, TDT4720. This pipeline has been optimized significantly and extended to support negation of all operands and single-precision input and output. New hardware has been designed for the decode/fetch unit, the register file, the compare/convert pipeline and the approximation tables. Division and square root is performed in software using Newton-Raphson iteration. The Verilog RTL implementation has been synthesized at 167 MHz using a 0.18 um standard cell library. The total area of the final implementation is 107 225 gates. The coprocessor has also been synthesized with the CPU. Test-programs have been run to verify that the coprocessor works correctly. A complete verification of the floating-point coprocessor, however, has not been performed due to limitations in time.nb_NO
dc.languageengnb_NO
dc.publisherInstitutt for datateknikk og informasjonsvitenskapnb_NO
dc.subjectntnudaimno_NO
dc.subjectSIF2 datateknikkno_NO
dc.subjectProgram- og informasjonssystemerno_NO
dc.titleImplementation of Floating-point Coprocessornb_NO
dc.typeMaster thesisnb_NO
dc.source.pagenumber110nb_NO
dc.contributor.departmentNorges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for datateknikk og informasjonsvitenskapnb_NO


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