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dc.contributor.authorGarvik, Harald
dc.contributor.authorWulff, Carsten
dc.contributor.authorYtterdal, Trond
dc.date.accessioned2018-01-29T13:33:52Z
dc.date.available2018-01-29T13:33:52Z
dc.date.created2017-10-31T15:36:42Z
dc.date.issued2017
dc.identifier.issn0886-5930
dc.identifier.urihttp://hdl.handle.net/11250/2480319
dc.description.abstractA noise-shaping SAR ADC implemented in 28 nm UTBB FDSOI is presented. A cascaded FIR-IIR loop filter topology is used, and implemented as an inverter-based switched-capacitor circuit. The loop filter also employs input buffers. To correct CDAC mismatch, an off-line calibration technique that estimates the CDAC calibration coefficients from a digitized test sequence is proposed and used. At 28 MS/s and Nyquist bandwidth of 1.75 MHz, the measured accuracy is 11.0 bit ENOB, and the Walden FOM 9.8 fJ/conv.-step.nb_NO
dc.language.isoengnb_NO
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)nb_NO
dc.titleAn 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimationnb_NO
dc.typeJournal articlenb_NO
dc.typePeer reviewednb_NO
dc.description.versionacceptedVersionnb_NO
dc.source.volume2017-Aprilnb_NO
dc.source.journalProceedings of the IEEE Custom Integrated Circuits Conferencenb_NO
dc.identifier.doi10.1109/CICC.2017.7993659
dc.identifier.cristin1509456
dc.relation.projectNorges forskningsråd: 237887nb_NO
dc.description.localcode© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.nb_NO
cristin.unitcode194,63,35,0
cristin.unitnameInstitutt for elektroniske systemer
cristin.ispublishedtrue
cristin.fulltextpostprint
cristin.qualitycode1


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