| dc.description.abstract | A device compact model is a mathematical description of a device, e.g. a transistor, in an
integrated circuit. Compact models are designed to be a part of a larger simulation, and
work together with a circuit model. For this reason errors in the device model will multiply
throughout the simulation. Device model validation is thus an important prerequisite for
simulating integrated circuits. In this thesis a comprehensive set of qualitative benchmark
tests is developed and presented.
In the course of device model testing, several hundred curves can be produced and have
to be evaluated in terms of whether they behave as expected from the laws of physics. To
facilitate this process a program that finds discontinuities in curves was implemented for
this thesis. | |
