| dc.description.abstract | The main motivation behind the work in this thesis is to develop analog modules suitable for in-probe ultrasound imaging applications. The area and power are the main concerns for these applications given the limited area of the probe which can be put on the catheter. The number of transducer on the ultrasound probe is continuously increasing due to high resolution requirements. The volumetric imaging is another reason for introduction of two dimensional arrays which again leads to a higher number of transducer in the probe. The electronics need to evolve so that more channels can be accommodated in the same amount of area as well as power consumption. In this work we have tried to come up with low-power, low-area modules like low-noise amplifier (LNA), beamformer which can be used for in-probe applications without sacrificing the performance. The first module we discuss about in this thesis is the LNA. A common-source amplifier (CSA) has been designed in 180 nm CMOS technology. To get a realistic estimation of amplifier performance, an electrical equivalent model of CMUT was used in the simulations. One of the most important performance parameter for the LNA is noise figure (NF) which has been kept less than 3 dB, while maintaining low area and power. Another important design parameter for the front-end amplifier is dynamic range. Dynamic range defines the maximum signal which can be processed faithfully by the receiver chain and noise dictates that minimum signal that can be detected by the system. In this work both these specifications have been optimized. An analytical solution is found to get the best noise figure. A noise figure (NF) of 3 dB is measured for a CMUT model with 10-30 MHz frequency range. The amplifier shows a dynamic range of 50 dB with 0.8% total harmonic distortion (THD) for the full scale input current of 7 µA peak-to-peak. The transducer in such systems is most often single-ended resulting in the front-end receiver electronics also being single-ended. This causes a high value of second harmonic distortion (HD2) for such circuits. It is possible to use pseudo-differential circuits to convert single-ended signal to differential, but it tends to take more area and power. In this thesis we propose a technique to reduce the HD2 generation. The second harmonic is essentially generated due to the second derivative of the trans-conductance (gm). If we try to keep gm constant in the desired operating region then the second derivative will diminish in value. It is done by connecting two transistors, one in triode region and another in saturation, by gate, source, and drain. The effective gm of the assembly can be designed to stay constant for a range of gate voltage. First an analytical proof of the concept is given using the MOSFET short-channel current equations. In second part of this work a CSA is designed using this technique and compared to another CSA having similar power consumption. Both the amplifiers are compared in terms of their AC, noise and transient response. It is observed that by using this technique an improvement of 9dB can be obtained in HD2 without significant impact on area, power or noise. The effect of process change is also analyzed and an external voltage can be used to tune out any operating point changes due to process. In the next part of thesis we discuss the beamformer design. The main principle behind the proposed beam former is the delay–and-sum technique. The incoming signal to the beamformer is continuously sampled and then delayed such that all the channels add in phase. An ARAM is used to sample the input. Two architectures for the ARAM are proposed. Both the architectures are switched-current (SI) memory based circuits. The difference between the architectures is the memory element. In the first architecture external capacitors are used to store the input signal while in the second architecture the traditional memory MOSFET gate capacitor is used to store the signal. The most important contribution by these beamformer is the current sharing concept. During the beamformer operation it can be easily noted that cells are read and written one at a time. Which means it is possible to share resources between read and write operation. There is a shared bias current between different memory cells. Since only one cell will be active at a time sharing the bias current can be easily achieved by using some additional switches. As a proof of concept, 16 channels each containing 16 memory cells have been implemented for both the architecture of the beamformer. The maximum input signal frequency is 10 MHz, and the sampling frequency is 25 MHz. The first architecture achieves SNR of 63 dB for summation of 16 channels and the current consumption per unit delay is 35.15 µA. The total power consumption of the beamformer including bias and digital control is 9 mA and area is 1.27 mm2. The second architecture achieves SNR of 60 dB after summation of 16 channels with each memory cell consuming 27µA. The total current consumption including bias and digital control is 7 mA and area is 1.3mm2. These architectures also contain a Class-AB voltage to current converter. The design is based on a quasi-floating-gate concept. This design can also be used as a variable gain amplifier or time-gain-compensation. | nb_NO |
