Ultra-Low Voltage SRAM in 130nm CMOS Process

Abstract

This thesis explores the viability of implementing a ultra-low voltage SRAM topology in a 130nm CMOS process for Atmel Norway AS. The topology supports voltage scaling between a subthreshold voltage of 400mV and a regular supply voltage of 1.2V. SRAM cells for ultra-low voltage operation and surrounding read and write circuitry is implemented using state of the art design techniques and literature.An asynchronous self-timed SRAM topology was implemented with conventional 6T SRAM cells and 10T SRAM cells specifically designed for ultra-low voltage operation. A small set of logic gates was also designed for ultra-low voltage operation to realize the surrounding read and write control circuitry. All building blocks were simulated with extracted parasitics from layout to get realistic simulation results. Corner and Monte Carlo simulations were used to show how temperature and process variations statistically affected the building blocks and their performance at both subthreshld and superthreshold voltages.Simulation results shows that the 10T cell is more robust at 400mV with a 60-70% larger static noise margin compared to the conventional 6T cell, but consumes more leakage power and is physically 64% larger. The 10T cell also needs more time to perform a read "0" operation since the single-ended nature of the SRAM cell requires a full bitline-swing to perform the read operation whereas the differential nature of the 6T cells speed up the read operation, but the offset voltage of the sense amplifier limits the speed gain at 400mV somewhat compared to at 1.2V. The read operation of the 6T cell causes a disturb voltage in the internal nodes of the SRAM cell and its magnitude is affected by the number of SRAM cells in the array, the width of the wordline signal and temperature. The impact of these factors are greater at high voltages, making it difficult to assess the yield in systems with voltage scaling. The 10T cell uses a read buffer to decouple the read and write operation and do not encounter this problem and this makes the 10T cell more predictable with voltage scaling and the safest choice for future implementations.The results also show that the power savings when moving from 1.2V to 400mV are withing the range of 5-18 times depending on the severity of process variations and temperature. The lowest power savings occur at high temperatures due to increased leakage currents. The largest savings occurs at low temperatures, but the performance is degraded to such a degree that the 10T implementation requires 5 32kHz clock cycles to complete a read "0" operation while the 6T implementation requires 3 at -40C in the SS process corner. To combat the extreme degradation in speed the supply voltage must be raised either permanently or through some kind of dynamic supply voltage compensation.