| dc.description.abstract | In this thesis, the author describes a propositional design for a DDR3 memory interface, for an existing H.264/AVC video transcoder. The design uses the Memory Interface Generator (MIG), a Xilinx IP, as an overlying memory controller interface. The different interfaces offered by the MIG are evaluated before the most fitting is chosen.The interface is designed for use on the KC705 Kintex-7 development kit, with a XC7K325T FPGA. Initial tests show promising results for the design, which is able to both write and read data to and from an external DDR3 SDRAM memory. The design has only been tested through simulation, and more extensive verification is needed before it can be completely evaluated as an alternative. The simulations use a memory model to produce realistic behavior of the memory.The interface uses two submodules, dedicated to writing and reading respectively. Both modules use data buffers, and the reading module has the ability of transferring data in different modes.Some room for improvement has been discovered, and the proposed design is thoroughly discussed. It has been successfully implemented, reporting an area utilization of 8,123 slices, with a maximum clock frequency of 308 MHz. | nb_NO |
