| dc.description.abstract | In this work, a model for estimating the energy consumption of different types ofrandom access memory(RAM) technologies, likely to be commercially available by2017, has been developed. The goal for this model has been to evaluate whichof the memory technologies that will be the most energy efficient in 2017. Thiswas done by building the model on the required energies to read or write a bit forthe different technologies. The memory technologies that have been modelled are:Dynamic RAM (DRAM), Static RAM (SRAM), Ferroelectric RAM (FeRAM),Magnetic RAM (MRAM), Spin-Torque Transfer Magnetic RAM (STT-MRAM)and Phase Change RAM (PCRAM).The volatile memory technologies, DRAM and SRAM, have been estimated tohave the lowest energy consumption if the memories are operated at a high dutycycle. However, if the duty cycle is reduced, the emerging non-volatile memorytechnologies become more energy efficient. The FeRAM was estimated to have thelowest power consumption when manufactured with the technology available today.And it has been estimated that with a duty cycle lower than 8.5 × E−4, FeRAMtechnology consumes less power than the SRAM, and with a duty cycle lower than1.6 × E−4, the FeRAM consumes less power than DRAM. When looking forwardtowards 2017, STT-MRAM was estimated to have the lowest power consumptionof the emerging memory technologies. It was estimated that the STT-MRAM consumesless power than SRAM for duty cycles lower than 2.3 × E−2 and consumesless power than the DRAM for duty cycles lower than 4.6 × E−4.An experimental set-up has been developed to validate the model, and a casestudy of some selected memories has been performed. With this case study somelimitations on the theoretical model have been pointed out. These limitations arebelieved to be reduced if the memories are embedded on chip. | nb_NO |
