dc.contributor.advisor | Ytterdal, Trond | nb_NO |
dc.contributor.author | Josephsen, Simon | nb_NO |
dc.date.accessioned | 2014-12-19T13:48:42Z | |
dc.date.accessioned | 2015-12-22T11:48:26Z | |
dc.date.available | 2014-12-19T13:48:42Z | |
dc.date.available | 2015-12-22T11:48:26Z | |
dc.date.created | 2013-09-19 | nb_NO |
dc.date.issued | 2013 | nb_NO |
dc.identifier | 649797 | nb_NO |
dc.identifier | ntnudaim:8707 | |
dc.identifier.uri | http://hdl.handle.net/11250/2370823 | |
dc.description.abstract | This master thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS technology. The proposed ADC operates with a supply voltage of 400 mV and the post-layout simulation resulted in a power consumption of 1.22 nW, which is among the best of the currently state-of-the-art ultra-low-power ADCs. Ultra-low power consumption is achieved by utilizing low power transistors with high threshold voltage to minimize leakage power, optimizing the control logic for sub-threshold operation and using a reference digital- to-analog converter with a monotonic switching procedure. The power consumption and resolution of the ADC is mainly limited by the comparator, however, an effective resolution of 8.16 bits is achieved, which results in a figure-of-merit of 4.27 fJ/conversion-step. | nb_NO |
dc.language | eng | nb_NO |
dc.publisher | Institutt for elektronikk og telekommunikasjon | nb_NO |
dc.title | An Ultra-Low Power SAR-ADC in 65 nm CMOS Technology | nb_NO |
dc.type | Master thesis | nb_NO |
dc.source.pagenumber | 80 | nb_NO |
dc.contributor.department | Norges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjon | nb_NO |