| dc.contributor.advisor | Ytterdal, Trond | nb_NO |
| dc.contributor.author | Eilertsen, Bård Egil | nb_NO |
| dc.date.accessioned | 2014-12-19T13:47:39Z | |
| dc.date.accessioned | 2015-12-22T11:46:44Z | |
| dc.date.available | 2014-12-19T13:47:39Z | |
| dc.date.available | 2015-12-22T11:46:44Z | |
| dc.date.created | 2012-11-08 | nb_NO |
| dc.date.issued | 2012 | nb_NO |
| dc.identifier | 566295 | nb_NO |
| dc.identifier.uri | http://hdl.handle.net/11250/2370517 | |
| dc.description.abstract | This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a sampling frequency on 50 MHz and has a maximum ENOB on 8.42 bit. Because of non-linearity will ENOB be input frequency dependent and degrade to 6.87 bit.The design is based on conventional current-mode SAR ADC operation, but with a new comparator design and time interleaving. Time interleaving is used to increase the sampling frequency 10 times.The circuit needs a high degree of matching to work properly. Sub-threshold operation in several current sources gives a high degree of uncertainty in the current value. Thus several calibration circuits are presented, but are not implemented. | nb_NO |
| dc.language | eng | nb_NO |
| dc.publisher | Institutt for elektronikk og telekommunikasjon | nb_NO |
| dc.subject | ntnudaim:7642 | no_NO |
| dc.subject | MTEL elektronikk | |
| dc.subject | Analog og blandet design | |
| dc.title | Current-Mode SAR-ADC In 180nm CMOS Technology | nb_NO |
| dc.type | Master thesis | nb_NO |
| dc.source.pagenumber | 81 | nb_NO |
| dc.contributor.department | Norges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjon | nb_NO |
