Modeling and Design of a Dual-Residue Pipelined ADC in 130nm CMOS

Abstract

A 9-bit 50M S/s dual-residue pipelined ADC is modeled and analyzed. Thefirst stage is a modified pipelined ADC stage, while the other stages uses aninterpolator to resolve the signals, the focus is on designing these stages. Thedual-residue architecture is insensitive to the gain of the residue amplifiers, andonly a matching between two amplifiers is necessary. Limiting parameters of theADC is the offset in the residue amplifiers, as well as gain mismatch betweenthe amplifiers. The maximum allowed offset voltage of the residue amplifier isVlsb/2 , and maximum allowable mismatch between the two residue amplifiers is 1/256 for a 9-bit ADC. Multiple amplifier topologies were discussed and the bestcandidate for residue amplification is found to be a zero-crossing based amplifier.With this type of amplifier the last 8 stages of the ADC has an estimated powerconsumption of 2.1mW.