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dc.contributor.advisorSvarstad, Kjetilnb_NO
dc.contributor.authorScheistrøen, Sigurd Røednb_NO
dc.date.accessioned2014-12-19T13:47:25Z
dc.date.accessioned2015-12-22T11:46:27Z
dc.date.available2014-12-19T13:47:25Z
dc.date.available2015-12-22T11:46:27Z
dc.date.created2012-11-08nb_NO
dc.date.issued2012nb_NO
dc.identifier565812nb_NO
dc.identifier.urihttp://hdl.handle.net/11250/2370464
dc.description.abstractThis report presents the design of an asynchronous Huffman decoder, implemented in the Balsa synthesis system. Power consumption, speed and area figures from the post layout design have been measured. In addition, a synchronous design was implemented in order to compare to the asynchronous design. When running at the same clock frequency, it was found that the asynchronous is faster and more power efficient than the synchronous design. However, at the maximum clock frequency for each design, the synchronous design has a higher throughput than the asynchronous design. It was also found that the asynchronous design has an area cost 10 times greater than the synchronous design. In theory, asynchronous circuits is faster and more power efficient than synchronous circuits, however this comes at an area and complexity overhead. In the case of the Huffman decoder implemented in this thesis, the benefits are not enough to compensate for the very large area increase.nb_NO
dc.languageengnb_NO
dc.publisherInstitutt for elektronikk og telekommunikasjonnb_NO
dc.subjectntnudaim:8286no_NO
dc.titleEvaluation of state-of-the-art Huffman decoding algorithms and their asynchronous implementation using BALSAnb_NO
dc.typeMaster thesisnb_NO
dc.source.pagenumber125nb_NO
dc.contributor.departmentNorges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjonnb_NO


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