| dc.description.abstract | The objective of this thesis was to design a power-efficient general purpose SAR ADC. The ADC's requirements were set by Energy Micro, favoring a very high performance-to-power ratio. The requirements are based on the present Energy Micro ADC, but with a 67% reduction in current consumption, a more modern CMOS technology of 90nm and a supply voltage of 1.2V.A full SAR ADC model was made using SPICE and VHDL code for the analog and digital sub-systems, respectively. The comparator was thoroughly designed and optimized, to achieve enough performance with as little power as possible. Then the total capacitor value of the sub-DAC was minimized, using extra reference voltages, minimizing the dynamic power consumption of the reference voltage generator. An asynchronous clock was also implemented, substantially increasing the available settling times of the comparator.The result was a very power-efficient SAR ADC, which fulfills the power-consumption requirement with 114$mu$J per conversion. Compared to other, similar SAR ADC's which has been researched, the ADC designed in this thesis is found to be very power-efficient. There might be some linearity problems in the ADC, partly from the transmission gates used as switches, but the overall design seems promising. | nb_NO |
