Vis enkel innførsel

dc.contributor.advisorFjeldly, Tor Anb_NO
dc.contributor.authorNilsen, Dag-Martinnb_NO
dc.date.accessioned2014-12-19T13:44:19Z
dc.date.accessioned2015-12-22T11:42:13Z
dc.date.available2014-12-19T13:44:19Z
dc.date.available2015-12-22T11:42:13Z
dc.date.created2010-09-04nb_NO
dc.date.issued2009nb_NO
dc.identifier348851nb_NO
dc.identifier.urihttp://hdl.handle.net/11250/2369445
dc.description.abstractA precise subthreshold potential model for the Quadruple FET (QuadFET) is presented in this thesis. The attempt of modeling the FinFET ("Fin" FET) in the same way failed, but the procedure of the attempt will still be presented in this thesis, and a conclusion of why this modeling did not work is given. For the QuadFET, an analytical solution of the inter-electrode potential distribution of the double-gate MOSFET (DG MOSFET) is used by performing a simple geometric scaling transformation. This is done with a high degree of precision due to structural similarities between the QuadFET and DG MOSFET, accounting for the dierence in gate control of the two devices. A parabolic approximation is then used to model the the cut-plane in the middle of the device, perpendicular to the electron ow from source to drain, of the QuadFET. The resulting analytical solution agrees very well with numerical simulations. For the FinFET, the same analytical solution of the DG MOSFET is used directly in the ground plane of the device, assuming that the electric elds going through the ground plane, into the thick substrate, is negligible. Conformal mapping is then used in the same plane as modeled in the QuadFET, that is the plane in the middle of the device, perpendicular to the electron ow from source to drain, resulting in an analytical solution of the FinFET. Since the potential curvature in the source-drain direction was neglected when making the three dimensional problem of the FinFET to a two dimensional one, the modeling failed. However, an attempt of modeling the transistor has been tested, the electrostatics of the device is better known, and a new way of modeling the device is briey discussed.nb_NO
dc.languageengnb_NO
dc.publisherInstitutt for elektronikk og telekommunikasjonnb_NO
dc.subjectntnudaimno_NO
dc.titleSubthreshold Potential Modeling of FinFET and QuadFETnb_NO
dc.typeMaster thesisnb_NO
dc.source.pagenumber62nb_NO
dc.contributor.departmentNorges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjonnb_NO


Tilhørende fil(er)

Thumbnail
Thumbnail

Denne innførselen finnes i følgende samling(er)

Vis enkel innførsel