| dc.description.abstract | Cryptographic algorithms, like the Advanced Encryption Standard, are frequently used in todays electronic appliances. Battery operated devices are increasingly popular, creating a demand for low energy solutions. As a microcontroller is incorporated in virtually all electronic appliances, the main objective in this thesis is to evaluate possible hardware implementations of AES and implement a solution optimized for low energy consumption, suited for incorporation in a microcontroller. A good cost/performance balance is also a design goal. An existing solution based on a 32 bit architecture with support for 128 bit keys was chosen as a basis and altered in order to lower area and energy consumption. The alterations yielded a 13.6% area reduction as well as 14.2% and 3.9% reduction in energy consumption in encryption and decryption mode, respectively. In addition to alterations in the datapath, low energy techniques like clock gating and numerical strength reduction has been applied in order to further lower the energy consumption. The proposed architecture was also extended in order to accommodate 256 bit keys. Although this increased the area by 9.2%, the power consumption was still reduced by 7.6% and 1.3% in en- and decryption, compared to the architecture chosen as basis. As AES is an algorithm which easily can be parallelized, a high throughput solution utilizing a 128 bit datapath was implemented. This AES module is able to process 372.4 Mbps at an operating frequency of 32 Mhz and is based on the same architecture as the 32 bit datapath solution. In addition, this implementation yielded excellent energy per encryption figures, 24.5% lower than the 32 bit solution. The alternative to performing AES in a dedicated hardware module is to perform it using software. In order to have a basis for comparison, a software solution optimized for 32 bit architectures was implemented. Simulations show that the energy consumption attained when performing AES in the proposed hardware module is approximately 2.3% of what a software solution would use. In addition, the throughput is increased by a factor of 25. The architecture proposed in this thesis combines relatively high throughput with modest demands to area and low energy per encryption. | nb_NO |
