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dc.contributor.advisorSæther, Trondnb_NO
dc.contributor.authorKaald, Runenb_NO
dc.date.accessioned2014-12-19T13:43:39Z
dc.date.accessioned2015-12-22T11:41:17Z
dc.date.available2014-12-19T13:43:39Z
dc.date.available2015-12-22T11:41:17Z
dc.date.created2010-09-03nb_NO
dc.date.issued2008nb_NO
dc.identifier347713nb_NO
dc.identifier.urihttp://hdl.handle.net/11250/2369165
dc.description.abstractA found state of the art Continuous Time Sigma Delta ADC is modelled and simulated for the presence of nonidealities. A comparison between two Excess Loop Delay compensation techniques is done, the digital differentiation technique was found to have lower swing at the last integrator, and did not need a gain-bandwidth induced delay sensitive summing amplifier. The detrimental influence of clock jitter is shown. Different DAC linearization techniques are discussed, the DWA algorithm was simulated and found to be the best choice for linearizing the DACs. Through high level modeling in Simulink and verification in the Cadence framework specifications for each building block was determined, a final simulation resulted in a SNDR of 76.3 dB.nb_NO
dc.languageengnb_NO
dc.publisherInstitutt for elektronikk og telekommunikasjonnb_NO
dc.subjectntnudaimno_NO
dc.titleModelling, Simulation and Implementation Considerations of High Speed Continuous Time Sigma Delta ADCnb_NO
dc.typeMaster thesisnb_NO
dc.source.pagenumber70nb_NO
dc.contributor.departmentNorges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjonnb_NO


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