Asynchronous DSP-core

Abstract

In this thesis multipliers with and without completion detection has been implemented using a 90 nm library to compare their properties reguarding completion time, area and power consumption. The structures tested were array and shiftand-add multipliers. The results were that when having larger bit-lengths, an asynchronous shift-and-add multiplier with completion detection can yield good completion times compared to a regular shift-and-add multiplier. Due to the large cost in area and power consumption for large array multipliers, an asynchonous shift-and add multiplier can be a slower, but better alternative in cases with restriction on area use and power consumption. The largest downside of the asynchronous design is the difficulty of verifying the design. Verification and design of an asynchronous circuit is tedious, and require accurate information on the timing of the technology used to be possible at all.