| dc.description.abstract | Since the birth of modern computer architecture, computer performance has witnessed an exponential growth, driven mainly by increased transistor density. In the last decade, performance advancement has become increasingly difficult as computers are limited by power budgets due to problems with heat dissipation. As transistor technology continues to advance, full utilization of the available silicon is becoming ever challenging. As a result, new avenues of design exploration have emerged to track down alternative routes for continued performance enhancement. One such research field concerns heterogeneous computer architectures, where cores that excel at different areas of computation are combined on a single chip in order to provide performance scaling and the assignment of process workloads to optimally suited hardware.
The SHMAC project applies heterogeneous research in a single ISA environment, where various hardware is deployed in a matrix of interchangeable tiles, with the only general purpose processor tile being an ARMv4T compliant Amber processor core.
While programs and operating systems have been proven to successfully run on the processor core, their practical use is limited by the available memory space as the core does not feature a memory management system.
This thesis introduces a memory management unit into the Amber processor, enabling virtual memory support at the hardware level. The final contribution is Vilma; an ARMv4T compliant core featuring a memory management unit, verified using hardware simulation and an assembly test suite. | |
