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dc.contributor.authorHammer, Per Birger Mikaelnb_NO
dc.date.accessioned2014-12-19T11:17:39Z
dc.date.available2014-12-19T11:17:39Z
dc.date.created2003-03-26nb_NO
dc.date.issued2003nb_NO
dc.identifier122442nb_NO
dc.identifier.urihttp://hdl.handle.net/11250/228338
dc.description.abstractThis thesis describes how PLL frequency synthesizers with cascaded and nested loop topologies can be used for the synthesis of low noise high frequency signals. Briefly explained, synthesizers with cascaded/nested loops combine a broadband PLL and a narrowband PLL. The broadband PLL makes it possible to obtain a low phase noise even from a relatively noisy VCO with an integrated resonator. The narrowband PLL, on the other hand, makes it possible to tune the output signal with a high frequency resolution. A necessary building block of this kind of synthesizer is a low frequency VCO having low noise. The thesis describes how this kind of VCO can be implemented by the use of low loss external resonator components and by employing tank enhancement for additional noise suppression. Tank enhancement is obtained by the use of centre tapped capacitors in order to reduce the tank impedance. A consequence of tank enhancement is that the transconductance of the gain element must be increased. The thesis also describes the design and evaluation of two fully integrated VCOs implemented in 0.35 µm CMOS. One of the VCOs had an operating freqency around 5.8 GHz. This VCO was also used as a building block of an experimental broadband PLL synthesizer having a target loop bandwidth of 25 MHz. Due to the large variations in VCO gain as a function of frequency, the PLL had a very narrow locking range. The other VCO had an operating frequency around 2.4 GHz and was designed with multiple parallel tuning elements. This configuration could be used to reduce the magnitude of the VCO gain by about 34 dB and to make the VCO less sensitive to noise from the charge pump or loop filter, while still maintaining a wide frequency tuning range. Another benefit of multiple tuning inputs would be that the variations in feedback tuning voltage could be reduced. This would reduce the variations in VCO gain and the mismatch between the source current and sink current of the charge pump and give a reduction of the reference spur level.nb_NO
dc.languageengnb_NO
dc.publisherFakultet for informasjonsteknologi, matematikk og elektroteknikknb_NO
dc.relation.ispartofseriesDr. ingeniøravhandling; 2003:19nb_NO
dc.titleNested loop radio frequency synthesizersnb_NO
dc.typeDoctoral thesisnb_NO
dc.source.pagenumber184nb_NO
dc.contributor.departmentNorges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikknb_NO
dc.description.degreedr.ing.nb_NO
dc.description.degreedr.ing.en_GB


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