Blar i Institutt for elektroniske systemer på emneord "Analog og blandet design"
Viser treff 1-8 av 8
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A 2.4 GHz Ultra-Low-Power Low-Noise-Amplifier
(Master thesis, 2010)In this thesis different aspects of general low power design and LNA-design have been studied. A new architecture for an ultra low power LNA is proposed and simple simulation results are presented. Simulations show that ... -
A 33 µW Sub-3 dB Noise Figure Low Noise Amplifier for Medical Ultrasound Applications
(Master thesis, 2011)The low noise amplifier is a critical part of most high performance ultrasoundreceivers, and is important for achieving high sensitivity and a wide dynamic range.By having a large gain in the low noise amplifier, the total ... -
A High Speed Low Cost Capacitor Reset Circuit
(Master thesis, 2011)This master thesis presents the investigation and design of a capacitor reset circuit. The circuit was implemented and simulated using a standard 0.35µm CMOS process. A capacitive load of 20pF should be reset at 0.1% ... -
A sub-1µW, 16kHz Current-Mode SAR-ADC for Neural Spike Recording
(Master thesis, 2011)This thesis presents an ultra-low-power 8-bit asynchronous current-modesuccessive approximation (SAR) ADC for single channel neuron spike recording.The novel design exploits current mode operating in weak inversion forhigh ... -
Current-Mode SAR-ADC In 180nm CMOS Technology
(Master thesis, 2012)This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a ... -
Design and Modelling of a High Resolution, Continuous-Time Delta-Sigma ADC: In-depth noise considerations and optimization
(Master thesis, 2011)This work documents the important design considerations and high--level development of an efficient Continuous-Time DS A/D converter for given system requirements. Projecting characteristics is especially essential in the ... -
Design of an Analog to Digital Converter with Superior Accuracy/Bandwidth vs. Power Ratio
(Master thesis, 2011)The objective of this thesis was to design a power-efficient general purpose SAR ADC. The ADC's requirements were set by Energy Micro, favoring a very high performance-to-power ratio. The requirements are based on the ... -
Modeling and Design of a Dual-Residue Pipelined ADC in 130nm CMOS
(Master thesis, 2012)A 9-bit 50M S/s dual-residue pipelined ADC is modeled and analyzed. Thefirst stage is a modified pipelined ADC stage, while the other stages uses aninterpolator to resolve the signals, the focus is on designing these stages. ...