Browsing NTNU Open by Author "Ytterdal, Trond"
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5.8GHz, 1W high efficiency Power Amplifier in 90nm CMOS
Tofte Røislien, Nina (Master thesis, 2009)PREFACE This master s thesis was written as the final step towards my master s degree, and it thereby marks the ending of my time at NTNU. The master s thesis was developed due to a proposal made by Texas Instruments, ... -
8-bit 50ksps ULV SAR ADC
Rosenberg, Fredrik Hilding (Master thesis, 2015)With the growing market of MCUs and embedded electronic powered by batteries, more energy efficient peripherals are needed. This project presents an Analog to Digital converter using ultra low supply voltage on transistor ... -
A 2.4 GHz Ultra-Low-Power Low-Noise-Amplifier
Midtflå, Nils Kåre (Master thesis, 2010)In this thesis different aspects of general low power design and LNA-design have been studied. A new architecture for an ultra low power LNA is proposed and simple simulation results are presented. Simulations show that ... -
A 33 µW Sub-3 dB Noise Figure Low Noise Amplifier for Medical Ultrasound Applications
Hansen, Hans Herman (Master thesis, 2011)The low noise amplifier is a critical part of most high performance ultrasoundreceivers, and is important for achieving high sensitivity and a wide dynamic range.By having a large gain in the low noise amplifier, the total ... -
A 65nm CMOS Front-end LNA for Medical Ultrasound Imaging with Feedback Employing Noise and Distortion Cancellation
Eriksrød, Jon Håvard (Master thesis, 2013)A high performance 67.2uW low power front-end Low Noise Amplifier (LNA) for ultrasound applications is proposed. The amplifier utilizes a balun based on a common-gate (CG) and a common-source (CS) combination. The CS-amplifier ... -
A Boost/Buck Power Supply Regulator with Superior Efficiency
Surdal, Helge Hollund (Master thesis, 2009)Several architectures are studied and a boost/buck power supply is proposed as to achieve superior efficiency. A boost and buck, dual mode converter core and drivers is implemented in a 180 nm cmos technology node and running ... -
A Chopper Offset-Stabilized Operational Amplifier in 22nm FD- SOI
Relling Berg, Simon (Master thesis, 2019)En chopper offset-stabilisert forsterker har blitt designet. Designet har blitt analysert ved bruk av Monte Carlo simuleringer pa skjema-niva med påførte mismatch og prosessvariasjoner. En 22nm transistor teknologi har ... -
A digital audio playback system with USB interface
Karlsen, Espen; Tørresen, Magne (Master thesis, 2009)A high performance sound card is designed and implemented using a USB enabled microcontroller and an external dataconverter. Data is retrieved either via USB or S/PDIF. The sampling clock is generated by a precision clock ... -
A fully differential capacitively-coupled high CMRR low-power chopper amplifier for EEG dry electrodes
Habibzadeh Tonekabony Shad, Erwin; Molinas Cabrera, Maria Marta; Ytterdal, Trond (Journal article; Peer reviewed, 2020)The use of dry electrodes is increasing rapidly. Since their impedance is high, there is a high impedance node at the connecting node between the electrode and amplifier. This leads to absorb powerline signal and high CMRR ... -
A Fully Differential Front End Charge Sampling Amplifier for Medical Ultrasound Imaging in 28nm FD-SOI Technology
Larsen, Endre (Master thesis, 2015)New generations of ultrasound imaging will contain thousands of receive and transmit elements in a single probe. This leads to challenges in analog front-end circuits concerning low power, low noise, low area consumption ... -
A High Speed Low Cost Capacitor Reset Circuit
Løvseth Finnøy, Torbjørn (Master thesis, 2011)This master thesis presents the investigation and design of a capacitor reset circuit. The circuit was implemented and simulated using a standard 0.35µm CMOS process. A capacitive load of 20pF should be reset at 0.1% ... -
A loadless 6T SRAM cell for sub- & near- threshold operation implementedin 28 nm FD-SOI CMOS technology
Låte, Even; Ytterdal, Trond; Aunet, Snorre (Journal article; Peer reviewed, 2018)Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ... -
A Novel Analog Front-End For ECG Acquisition
Theie, Øyvind Bjørkøy (Master thesis, 2012)A complete analog front-end for portable ECG systems in 65nm technology was modeled and simulated using Cadence Virtuoso. All the required components for the AFE was incorporated into the continuous-time loop filter of a ... -
A sub-1µW, 16kHz Current-Mode SAR-ADC for Neural Spike Recording
Haaheim, Bård (Master thesis, 2011)This thesis presents an ultra-low-power 8-bit asynchronous current-modesuccessive approximation (SAR) ADC for single channel neuron spike recording.The novel design exploits current mode operating in weak inversion forhigh ... -
Amplifier for optimal reflection Coefficient of ultrasound transducer: A study of op amp based circuits for ultrasound transducers, targeted for low reflection Coefficient, high gain, and low noise
Mainou Gomez, José Francisco (Master thesis, 2012)Reverberation is defined as equally-spaced, bright linear echoes resulting from reflection from specular-type interfaces. They are provoked by the acoustic Impedance change between the tissue and transducer front surface. ... -
An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation
Garvik, Harald; Wulff, Carsten; Ytterdal, Trond (Journal article; Peer reviewed, 2017)A noise-shaping SAR ADC implemented in 28 nm UTBB FDSOI is presented. A cascaded FIR-IIR loop filter topology is used, and implemented as an inverter-based switched-capacitor circuit. The loop filter also employs input ... -
An energy efficient noise-shaping SAR ADC in 28 nm FDSOI
Garvik, Harald (Master thesis, 2015)In a noise-shaping SAR ADC, oversampling and noise shaping are used to increase the conversion accuracy beyond that the SAR exhibits alone. To implement the noise shaping, the residue voltage present at the SAR DAC plates ... -
An Ultra-Low Power SAR-ADC in 65 nm CMOS Technology
Josephsen, Simon (Master thesis, 2013)This master thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS technology. The proposed ADC ... -
An Ultra-Low Power SAR-ADC in 65 nm CMOS Technology
Josephsen, Simon (Master thesis, 2013)This master?s thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS technology. The proposed ADC ... -
An Ultra-Low Voltage and Low-Energy Level Shifter in 28 nm UTBB-FDSOI
Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre (Journal article; Peer reviewed, 2018)Abstract—A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used ...