Blar i NTNU Open på forfatter "Wulff, Carsten"
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An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation
Garvik, Harald; Wulff, Carsten; Ytterdal, Trond (Journal article; Peer reviewed, 2017)A noise-shaping SAR ADC implemented in 28 nm UTBB FDSOI is presented. A cascaded FIR-IIR loop filter topology is used, and implemented as an inverter-based switched-capacitor circuit. The loop filter also employs input ... -
An energy efficient noise-shaping SAR ADC in 28 nm FDSOI
Garvik, Harald (Master thesis, 2015)In a noise-shaping SAR ADC, oversampling and noise shaping are used to increase the conversion accuracy beyond that the SAR exhibits alone. To implement the noise shaping, the residue voltage present at the SAR DAC plates ... -
Compensation of Threshold Voltage for Process and Temperature Variations in 28nm UTBB FDSOI
Strandvik, Erlend (Master thesis, 2015)As technology scales down in order to meet demands of more computing power per area, a variety of challenges emerge. Devices with channel lengths of a few nano meters require atomic precision when they are manufactured. ... -
Design and implementation of a 0.01 mm² current-mode temperature sensor in 22 nm FD-SOI with a sensing range of -40 °C to 125 °C and 6.3 nW at 0.8 V
Ege, Jonathan Sæthre; Egge, Sondre Hånes (Master thesis, 2023)Dette arbeidet presenterer en temperatursensor implementert i en 22 nm Full- stendig Depletert Silikon på Isolator (FD-SOI) teknologi av GlobalFoundries. Arbeidet bygger på grunnarbeidet fra vårt tidligere prosjektarbeid ... -
Design and implementation of a 0.01 mm² current-mode temperature sensor in 22 nm FD-SOI with a sensing range of -40 °C to 125 °C and 6.3 nW at 0.8 V
Ege, Jonathan Sæthre; Egge, Sondre Hånes (Master thesis, 2023)Dette arbeidet presenterer en temperatursensor implementert i en 22 nm Full- stendig Depletert Silikon på Isolator (FD-SOI) teknologi av GlobalFoundries. Arbeidet bygger på grunnarbeidet fra vårt tidligere prosjektarbeid ... -
Design and Optimization of a 2.4 GHz, 30 dBm Power Amplifier Utilizing Drain Modulation for Enhanced Efficiency
Olsen, Mathias (Master thesis, 2023)This thesis presents a study on the design and performance analysis of power amplifiers (PAs) utilizing envelope tracking (ET), or drain modulation, techniques to enhance their efficiency. The focus of this research is ... -
Design Considerations for a Low-Power Control-Bounded A/D Converter
Feyling, Fredrik Esp (Master thesis, 2021)Kontrollbegrenset analog-til-digital omforming (control-bounded ADC) er et nylig introdusert konsept som skiller seg fundamentalt fra de fleste konvensjonelle omformingsarkitekturer. De lovende egenskapene ved disse ... -
Development and Optimization of a Contact Tracing Wearable
Aalien, Martin Gulbrandsen (Master thesis, 2021)Markedet for kroppsbårne elektroniske enheter for helse- og aktivitets-monitorering er i kraftig utvikling. Nylig har det fått oppmerksomhet som en alternativ måte å gjennomføre smittesporing på for å redusere spredningen ... -
Efficient ADCs for nano-scaleCMOS Technology
Wulff, Carsten (Doktoravhandlinger ved NTNU, 1503-8181; 2008:292, Doctoral thesis, 2008) -
Improving Accuracy of MCPD Distance Measurements
Suarez Lojan, Johan Nicolas (Master thesis, 2023)The distance measurements obtained with Multi-Carrier Phase Difference algorithms exhibit a bias in the estimated values. This work aims to explore ways to reduce the effects of the bias in the measurements. Initially, an ... -
Mapping Wireless Network Nodes Automatically to a Predefined Set of Positions using Distance Measurements
Robstad, Erik Vincent Røgenes (Master thesis, 2021)Abstract will be available on 2024-06-16 -
Noise transfer functions and loop filters especially suited for noise-shaping SAR ADCs
Garvik, Harald; Wulff, Carsten; Ytterdal, Trond (Journal article; Peer reviewed, 2016)Oversampling and noise-shaping have in recent years been introduced to SAR ADCs to improve the conversion accuracy. Similar to delta-sigma ADCs, this is done by means of a feedback loop containing a loop filter. In this ... -
Ultra Low Power Frequency Synthesizer
Nielsen, Cole (Master thesis, 2020)En strøm- og jitter FOM state of art integer-N all digital faselåst loop (ADPLL) frekvenssynteser implementert i en kommersielt tilgjengelig 22nm FD-SOI-prosess blir presentert i denne artikkelen. Oppnådd var et strømforbruk ... -
Ultra-Low Power SAR-ADC in 28nm CMOS Technology
Nornes, Thomas Hanssen (Master thesis, 2015)This thesis presents an improved ultra-low power 10-bit 1 kS/s successive approximation (SAR) analog to digital converter (ADC) building on the work performed by Simon Josepshen in 2013. The improved ADC has a supply of ...