• BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing 

      Umuroglu, Yaman; Rasnayake, Lahiru; Själander, Magnus (Chapter, 2018)
      Matrix-matrix multiplication is a key computational kernel for numerous applications in science and engineering, with ample parallelism and data locality that lends itself well to high-performance implementations. Many ...
    • Challenges and solutions in creating a RISC-V computing platform 

      Monsen, Kristoffer Venæs (Master thesis, 2019)
      I denne masteroppgaven beskriver vi implementasjonen av et datasystem som baserer seg på RISC-V instruksjonssettet. Ved å gjenbruke eksisterende maskinvaremoduler fra Cobham Gaislers åpent tilgjengelige GRLIB IP core library ...
    • Clairvoyance: Look-Ahead Compile-Time Scheduling 

      Tran, Kim-Anh; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Spiliopoulos, Vasileios; Kaxiras, Stefanos; Jimborean, Alexandra (Chapter, 2017)
      To enhance the performance of memory-bound applications, hardware designs have been developed to hide memory latency, such as the out-of-order (OoO) execution engine, at the price of increased energy consumption. Contemporary ...
    • Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design 

      Tran, Kim-anh; Sakalis, Christos; Själander, Magnus; Ros, Alberto; Kaxiras, Stefanos; Jimborean, Alexandra (Chapter, 2020)
      Out-of-order processors heavily rely on speculation to achieve high performance, allowing instructions to bypass other slower instructions in order to fully utilize the processor's resources. Speculatively executed ...
    • Combining the SHA and ELD3 techniques to achieve energy-efficient data cache accesses 

      Asjad, Salahuddin (Master thesis, 2017)
      In recent years, CPU performance has become energy constrained. If performance is to continue increasing, new methods for creating more energy efficient CPUs will have to be explored. Current computing systems use complex ...
    • Creation of a software programmable hardware interface 

      Jordet, Ludvig Samuelsen (Master thesis, 2019)
      Gjennom arbeidet med denne oppgaven ble det laget to forskjellige maskinvaredesign. Den første var en konfigurerbar komponent som implementerte b˚ade UART, SPI og I2C. Denne ble laget for ˚a finne ut hvorvidt dette kunne ha ...
    • DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore 

      Saha, Sangeet; Chakraborty, Shounak; Agarwal, Sukarn; Gangopadhyay, Rahul; Själander, Magnus; McDonald, K. (Peer reviewed; Journal article, 2023)
      Enhancing result-accuracy in approximate computing (AC) based real-time systems, without violating power constraints of the underlying hardware, is a challenging problem. Execution of such AC real-time applications can be ...
    • Do Not Predict – Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation 

      Sakalis, Christos; Chowdhury, Zamshed; Wadle, Shayne; Akturk, Ismail; Ros, Alberto; Själander, Magnus; Kaxiras, Stefanos; Karpuzcu, Ulya (Chapter, 2021)
      Recent architectural approaches that address speculative side-channel attacks aim to prevent software from exposing the microarchitectural state changes of transient execution. The Delay-on-Miss technique is one such ...
    • Efficient invisible speculative execution through selective delay and value prediction 

      Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Jimborean, Alexandra; Själander, Magnus (Journal article; Peer reviewed, 2019)
      Speculative execution, the base on which modern high-performance general-purpose CPUs are built on, has recently been shown to enable a slew of security attacks. All these attacks are centered around a common set of ...
    • Estimating Tail-Latency of Latency-Sensitive Workloads 

      Eggan, Alf Martin; Eggan, Karl Andreas (Master thesis, 2019)
      Mange av arbeidsoppgavene som behandles i dagens datasentre er følsomme for forsinkelse, og krever at brukere har en tilfredsstillende opplevelse, noe som gjør energibesparing til en utfordring, som følge av strenge krav ...
    • Evaluating FIFO-based Instruction Scheduling Techniques using FPGAs 

      Metz, David Christoph; Jellum, Erling Rennemo (Master thesis, 2020)
      The performance advantage of out-of-order processors stems from their ability to extract more instruction-level parallelism (ILP) and memory-level parallelism (MLP) than in-order cores. This is largely the benefit of the ...
    • Evaluating FIFO-based Instruction Scheduling Techniques using FPGAs 

      Metz, David Christoph; Jellum, Erling Rennemo (Master thesis, 2020)
      The performance advantage of out-of-order processors stems from their ability to extract more instruction-level parallelism (ILP) and memory-level parallelism (MLP) than in-order cores. This is largely the benefit of the ...
    • Evaluating performance impact of performing computations on storage nodes - Batch on Eos Extra Resources (BEER) 

      Tollefsen, Håvard (Master thesis, 2018)
      The Batch on EOS Extra Resources (BEER) project is a response to observations of available computing resources on EOS storage system. BEER introduces sharing computing resources between storage and compute nodes. The project ...
    • Evaluating the Potential Applications of Quaternary Logic for Approximate Computing 

      Sakalis, Christos; Jimborean, Alexandra; Kaxiras, Stefanos; Själander, Magnus (Journal article, 2019)
      There exist extensive ongoing research efforts on emerging atomic-scale technologies that have the potential to become an alternative to today’s complementary metal--oxide--semiconductor technologies. A common feature among ...
    • Exploring Efficient Accelerator-Core Integration Strategies: A Case Study of BISMO in Chipyard 

      Harnes, Vetle Kristaver Widnes (Master thesis, 2023)
      Ytelsen til enkeltkjerner har stagnert de siste årene, som følge av slutten på Dennard skalering og minneveggen. For å omgå dette, har maskinvare designere introdusert spesialiserte akseleratorer som utmerker seg i spesifikke ...
    • Flatspin: A large-scale artificial spin ice simulator 

      Jensen, Johannes Høydahl; Strømberg, Anders; Lykkebø, Odd Rune Strømmen; Penty, Arthur George; Lealiaert, Jonathan; Själander, Magnus; Folven, Erik; Tufte, Gunnar (Journal article; Peer reviewed, 2022)
      We present flatspin, a novel simulator for systems of interacting mesoscopic spins on a lattice, also known as artificial spin ice (ASI). A generalization of the Stoner-Wohlfarth model is introduced, and combined with a ...
    • Ghost loads: what is the cost of invisible speculation? 

      Sakalis, Christos; Alipour, Mehdi; Ros, Alberto; Jimborean, Alexandra; Kaxiras, Stefanos; Själander, Magnus (Chapter, 2019)
      Speculative execution is necessary for achieving high performance on modern general-purpose CPUs but, starting with Spectre and Meltdown, it has also been proven to cause severe security flaws. In case of a misspeculation, ...
    • Implementation and Evaluation of Data Filter Cache for a RISC-V processor 

      Plotkin, Valentin (Master thesis, 2020)
      Hovedmålet av det moderne prosessorutvikling er å forbedre energiforbruk. Minnesystemet, som er ansvarlig for en betydeling del av det totale energiforbruket er en naturlig kandidat for å anvende teknikker for energisparing. Som ...
    • Implementing Data Cache Access Memoization (DCAM) in hardware to measure L1 DC and DTLB energy efficiency 

      Vedvik, Edgar (Master thesis, 2019)
      Nivå-1 data-hurtiglager (L1 DC) og mellomlager for dataoversetting (DTLB) er essensielle i nåtidens minnehierarki for å gi raskere tilgang til data og redusere antall ventesykluser. Disse strukturene bli aksessert ofte, ...
    • Implementing RVSDG as a dialect of MLIR 

      Bjørstad, Halvor (Master thesis, 2023)
      Slutten på Dennard-skaleringen og det påfølgende skiftet til flerkjernede og heterogene prosessorarkitekturer har flyttet ansvaret for å øke ytelsen til programvare over på programmerere og verktøyene deres. Et behov for ...