Blar i NTNU Open på forfatter "Ros, Alberto"

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    • Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design 

      Tran, Kim-anh; Sakalis, Christos; Själander, Magnus; Ros, Alberto; Kaxiras, Stefanos; Jimborean, Alexandra (Chapter, 2020)
      Out-of-order processors heavily rely on speculation to achieve high performance, allowing instructions to bypass other slower instructions in order to fully utilize the processor's resources. Speculatively executed ...

    • Do Not Predict – Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation 

      Sakalis, Christos; Chowdhury, Zamshed; Wadle, Shayne; Akturk, Ismail; Ros, Alberto; Själander, Magnus; Kaxiras, Stefanos; Karpuzcu, Ulya (Chapter, 2021)
      Recent architectural approaches that address speculative side-channel attacks aim to prevent software from exposing the microarchitectural state changes of transient execution. The Delay-on-Miss technique is one such ...

    • Efficient invisible speculative execution through selective delay and value prediction 

      Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Jimborean, Alexandra; Själander, Magnus (Journal article; Peer reviewed, 2019)
      Speculative execution, the base on which modern high-performance general-purpose CPUs are built on, has recently been shown to enable a slew of security attacks. All these attacks are centered around a common set of ...

    • Ghost loads: what is the cost of invisible speculation? 

      Sakalis, Christos; Alipour, Mehdi; Ros, Alberto; Jimborean, Alexandra; Kaxiras, Stefanos; Själander, Magnus (Chapter, 2019)
      Speculative execution is necessary for achieving high performance on modern general-purpose CPUs but, starting with Spectre and Meltdown, it has also been proven to cause severe security flaws. In case of a misspeculation, ...

    • Temporarily Unauthorized Stores: Write First, Ask for Permission Later 

      Cebrian, Juan Manuel; Jahre, Magnus; Ros, Alberto (Chapter, 2024)
      x86 processors implement a total store order (x86-TSO) consistency model, which requires stores to update memory in a sequenced manner. The latency of stores is then hidden by the store buffer (SB), which holds stores until ...

    • Understanding Selective Delay as a Method for Efficient Secure Speculative Execution 

      Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Jimborean, Alexandra; Själander, Magnus (Peer reviewed; Journal article, 2020)
      Since the introduction of Meltdown and Spectre, the research community has been tirelessly working on speculative side-channel attacks and on how to shield computer systems from them. To ensure that a system is protected ...