Data Fields | |
union { | |
volatile uint8_t u8 | |
volatile uint16_t u16 | |
volatile uint32_t u32 | |
} | PORT [32U] |
uint32_t | RESERVED0 [864U] |
volatile uint32_t | TER |
uint32_t | RESERVED1 [15U] |
volatile uint32_t | TPR |
uint32_t | RESERVED2 [15U] |
volatile uint32_t | TCR |
uint32_t | RESERVED3 [29U] |
volatile uint32_t | IWR |
volatile const uint32_t | IRR |
volatile uint32_t | IMCR |
uint32_t | RESERVED4 [43U] |
volatile uint32_t | LAR |
volatile const uint32_t | LSR |
uint32_t | RESERVED5 [6U] |
volatile const uint32_t | PID4 |
volatile const uint32_t | PID5 |
volatile const uint32_t | PID6 |
volatile const uint32_t | PID7 |
volatile const uint32_t | PID0 |
volatile const uint32_t | PID1 |
volatile const uint32_t | PID2 |
volatile const uint32_t | PID3 |
volatile const uint32_t | CID0 |
volatile const uint32_t | CID1 |
volatile const uint32_t | CID2 |
volatile const uint32_t | CID3 |
volatile const uint32_t CID0 |
volatile const uint32_t CID1 |
volatile const uint32_t CID2 |
volatile const uint32_t CID3 |
volatile uint32_t IMCR |
volatile const uint32_t IRR |
volatile uint32_t IWR |
volatile uint32_t LAR |
volatile const uint32_t LSR |
volatile const uint32_t PID0 |
volatile const uint32_t PID1 |
volatile const uint32_t PID2 |
volatile const uint32_t PID3 |
volatile const uint32_t PID4 |
volatile const uint32_t PID5 |
volatile const uint32_t PID6 |
volatile const uint32_t PID7 |
volatile { ... } PORT[32U] |
uint32_t RESERVED0[864U] |
uint32_t RESERVED1[15U] |
uint32_t RESERVED2[15U] |
uint32_t RESERVED3[29U] |
uint32_t RESERVED4[43U] |
uint32_t RESERVED5[6U] |
volatile uint32_t TCR |
volatile uint32_t TER |
volatile uint32_t TPR |
volatile uint16_t u16 |
volatile uint32_t u32 |
volatile uint8_t u8 |