Core configuration file. More...
Core configuration file.
#define ADVANCED_ADVDATA_SUPPORT 0 |
#define APDU_BUFF_SIZE 250 |
#define APP_BUTTON_CONFIG_DEBUG_COLOR 0 |
#define APP_BUTTON_CONFIG_INFO_COLOR 0 |
#define APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL 3 |
#define APP_BUTTON_CONFIG_LOG_ENABLED 0 |
#define APP_BUTTON_CONFIG_LOG_LEVEL 3 |
#define APP_FIFO_ENABLED 1 |
#define APP_GPIOTE_ENABLED 0 |
#define APP_PWM_ENABLED 0 |
#define APP_SCHEDULER_ENABLED 0 |
#define APP_SCHEDULER_WITH_PAUSE 0 |
#define APP_SCHEDULER_WITH_PROFILER 0 |
#define APP_SDCARD_ENABLED 1 |
#define APP_SDCARD_FREQ_DATA 33554432 |
#define APP_SDCARD_FREQ_INIT 33554432 |
#define APP_SDCARD_SPI_INSTANCE 1 |
#define APP_TIMER_CONFIG_DEBUG_COLOR 0 |
#define APP_TIMER_CONFIG_INFO_COLOR 0 |
#define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3 |
#define APP_TIMER_CONFIG_IRQ_PRIORITY 6 |
#define APP_TIMER_CONFIG_LOG_ENABLED 0 |
#define APP_TIMER_CONFIG_LOG_LEVEL 3 |
#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10 |
#define APP_TIMER_CONFIG_RTC_FREQUENCY 0 |
#define APP_TIMER_CONFIG_SWI_NUMBER 0 |
#define APP_TIMER_CONFIG_USE_SCHEDULER 0 |
#define APP_TIMER_ENABLED 1 |
#define APP_TIMER_KEEPS_RTC_ACTIVE 0 |
#define APP_TIMER_SAFE_WINDOW_MS 300000 |
#define APP_TIMER_WITH_PROFILER 0 |
#define APP_UART_DRIVER_INSTANCE 0 |
#define APP_UART_ENABLED 1 |
#define APP_USBD_AUDIO_ENABLED 0 |
#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0 |
#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0 |
#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0 |
#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3 |
#define APP_USBD_CDC_ACM_ENABLED 0 |
#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1 |
#define APP_USBD_CONFIG_DEBUG_COLOR 0 |
#define APP_USBD_CONFIG_DESC_STRING_SIZE 31 |
#define APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED 1 |
#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1 |
#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32 |
#define APP_USBD_CONFIG_INFO_COLOR 0 |
#define APP_USBD_CONFIG_LOG_ENABLED 0 |
#define APP_USBD_CONFIG_LOG_LEVEL 3 |
#define APP_USBD_CONFIG_MAX_POWER 100 |
#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1 |
#define APP_USBD_CONFIG_SELF_POWERED 1 |
#define APP_USBD_CONFIG_SOF_HANDLING_MODE 2 |
#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0 |
#define APP_USBD_DEVICE_VER_MAJOR 1 |
#define APP_USBD_DEVICE_VER_MINOR 0 |
#define APP_USBD_DEVICE_VER_SUB 0 |
#define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0 |
#define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0 |
#define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0 |
#define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3 |
#define APP_USBD_ENABLED 0 |
#define APP_USBD_HID_DEFAULT_IDLE_RATE 0 |
#define APP_USBD_HID_ENABLED 0 |
#define APP_USBD_HID_GENERIC_ENABLED 0 |
#define APP_USBD_HID_KBD_ENABLED 0 |
#define APP_USBD_HID_MOUSE_ENABLED 0 |
#define APP_USBD_HID_REPORT_IDLE_TABLE_SIZE 4 |
#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0 |
#define APP_USBD_MSC_CONFIG_INFO_COLOR 0 |
#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0 |
#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3 |
#define APP_USBD_MSC_ENABLED 0 |
#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0 |
#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0 |
#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0 |
#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3 |
#define APP_USBD_PID 0 |
#define APP_USBD_STRING_CONFIGURATION_EXTERN 0 |
#define APP_USBD_STRING_ID_CONFIGURATION 4 |
#define APP_USBD_STRING_ID_MANUFACTURER 1 |
#define APP_USBD_STRING_ID_PRODUCT 2 |
#define APP_USBD_STRING_ID_SERIAL 3 |
#define APP_USBD_STRING_SERIAL APP_USBD_STRING_DESC("000000000000") |
#define APP_USBD_STRING_SERIAL_EXTERN 0 |
#define APP_USBD_STRINGS_CONFIGURATION APP_USBD_STRING_DESC("Default configuration") |
#define APP_USBD_STRINGS_LANGIDS APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US) |
#define APP_USBD_STRINGS_MANUFACTURER APP_USBD_STRING_DESC("Nordic Semiconductor") |
#define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0 |
#define APP_USBD_STRINGS_PRODUCT APP_USBD_STRING_DESC("nRF52 USB Product") |
#define APP_USBD_STRINGS_PRODUCT_EXTERN 0 |
#define APP_USBD_STRINGS_USER X(APP_USER_1, , APP_USBD_STRING_DESC("User 1")) |
#define APP_USBD_VID 0 |
#define BLE_ADV_BLE_OBSERVER_PRIO 1 |
#define BLE_ADVERTISING_ENABLED 1 |
#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_ANCS_C_ENABLED 0 |
#define BLE_ANS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_ANS_C_ENABLED 0 |
#define BLE_BAS_BLE_OBSERVER_PRIO 2 |
#define BLE_BAS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_BAS_C_ENABLED 0 |
#define BLE_BAS_CONFIG_DEBUG_COLOR 0 |
#define BLE_BAS_CONFIG_INFO_COLOR 0 |
#define BLE_BAS_CONFIG_LOG_ENABLED 0 |
#define BLE_BAS_CONFIG_LOG_LEVEL 3 |
#define BLE_BAS_ENABLED 0 |
#define BLE_BPS_BLE_OBSERVER_PRIO 2 |
#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1 |
#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0 |
#define BLE_CSCS_BLE_OBSERVER_PRIO 2 |
#define BLE_CSCS_ENABLED 0 |
#define BLE_CTS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_CTS_C_ENABLED 0 |
#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1 |
#define BLE_DFU_BLE_OBSERVER_PRIO 2 |
#define BLE_DFU_ENABLED 0 |
#define BLE_DFU_SOC_OBSERVER_PRIO 1 |
#define BLE_DIS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_DIS_ENABLED 0 |
#define BLE_DTM_ENABLED 0 |
#define BLE_GLS_BLE_OBSERVER_PRIO 2 |
#define BLE_GLS_ENABLED 0 |
#define BLE_HIDS_BLE_OBSERVER_PRIO 2 |
#define BLE_HIDS_ENABLED 0 |
#define BLE_HRS_BLE_OBSERVER_PRIO 2 |
#define BLE_HRS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_HRS_C_ENABLED 0 |
#define BLE_HRS_ENABLED 0 |
#define BLE_HTS_BLE_OBSERVER_PRIO 2 |
#define BLE_HTS_ENABLED 0 |
#define BLE_IAS_BLE_OBSERVER_PRIO 2 |
#define BLE_IAS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_IAS_C_ENABLED 0 |
#define BLE_IAS_CONFIG_DEBUG_COLOR 0 |
#define BLE_IAS_CONFIG_INFO_COLOR 0 |
#define BLE_IAS_CONFIG_LOG_ENABLED 0 |
#define BLE_IAS_CONFIG_LOG_LEVEL 3 |
#define BLE_IAS_ENABLED 0 |
#define BLE_LBS_BLE_OBSERVER_PRIO 2 |
#define BLE_LBS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_LBS_C_ENABLED 0 |
#define BLE_LBS_ENABLED 0 |
#define BLE_LLS_BLE_OBSERVER_PRIO 2 |
#define BLE_LLS_ENABLED 0 |
#define BLE_LNS_BLE_OBSERVER_PRIO 2 |
#define BLE_NFC_SEC_PARAM_BOND 1 |
#define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1 |
#define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1 |
#define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1 |
#define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1 |
#define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16 |
#define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7 |
#define BLE_NUS_BLE_OBSERVER_PRIO 2 |
#define BLE_NUS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_NUS_C_ENABLED 0 |
#define BLE_NUS_CONFIG_DEBUG_COLOR 3 |
#define BLE_NUS_CONFIG_INFO_COLOR 0 |
#define BLE_NUS_CONFIG_LOG_ENABLED 1 |
#define BLE_NUS_CONFIG_LOG_LEVEL 4 |
#define BLE_NUS_ENABLED 1 |
#define BLE_OTS_BLE_OBSERVER_PRIO 2 |
#define BLE_OTS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_RACP_ENABLED 0 |
#define BLE_RSCS_BLE_OBSERVER_PRIO 2 |
#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2 |
#define BLE_RSCS_C_ENABLED 0 |
#define BLE_RSCS_ENABLED 0 |
#define BLE_TPS_BLE_OBSERVER_PRIO 2 |
#define BLE_TPS_ENABLED 0 |
#define BSP_BTN_BLE_ENABLED 1 |
#define BSP_BTN_BLE_OBSERVER_PRIO 1 |
#define BUTTON_ENABLED 1 |
#define BUTTON_HIGH_ACCURACY_ENABLED 0 |
#define CC_STORAGE_BUFF_SIZE 64 |
#define CLOCK_CONFIG_DEBUG_COLOR 0 |
#define CLOCK_CONFIG_INFO_COLOR 0 |
#define CLOCK_CONFIG_IRQ_PRIORITY 6 |
#define CLOCK_CONFIG_LF_CAL_ENABLED 0 |
#define CLOCK_CONFIG_LF_SRC 1 |
#define CLOCK_CONFIG_LOG_ENABLED 0 |
#define CLOCK_CONFIG_LOG_LEVEL 3 |
#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0 |
#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0 |
#define COMP_CONFIG_DEBUG_COLOR 0 |
#define COMP_CONFIG_HYST 0 |
#define COMP_CONFIG_INFO_COLOR 0 |
#define COMP_CONFIG_INPUT 0 |
#define COMP_CONFIG_IRQ_PRIORITY 6 |
#define COMP_CONFIG_ISOURCE 0 |
#define COMP_CONFIG_LOG_ENABLED 0 |
#define COMP_CONFIG_LOG_LEVEL 3 |
#define COMP_CONFIG_MAIN_MODE 0 |
#define COMP_CONFIG_REF 1 |
#define COMP_CONFIG_SPEED_MODE 2 |
#define COMP_ENABLED 0 |
#define CRC16_ENABLED 1 |
#define CRC32_ENABLED 0 |
#define ECC_ENABLED 0 |
#define EGU_ENABLED 0 |
#define FDS_BACKEND 2 |
#define FDS_CRC_CHECK_ON_READ 0 |
#define FDS_CRC_CHECK_ON_WRITE 0 |
#define FDS_ENABLED 1 |
#define FDS_MAX_USERS 4 |
#define FDS_OP_QUEUE_SIZE 4 |
#define FDS_VIRTUAL_PAGE_SIZE 1024 |
#define FDS_VIRTUAL_PAGES 3 |
#define FDS_VIRTUAL_PAGES_RESERVED 0 |
#define GPIOTE_CONFIG_DEBUG_COLOR 0 |
#define GPIOTE_CONFIG_INFO_COLOR 0 |
#define GPIOTE_CONFIG_IRQ_PRIORITY 7 |
#define GPIOTE_CONFIG_LOG_ENABLED 0 |
#define GPIOTE_CONFIG_LOG_LEVEL 3 |
#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4 |
#define GPIOTE_ENABLED 1 |
#define HARDFAULT_HANDLER_ENABLED 0 |
#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 |
#define HCI_MEM_POOL_ENABLED 0 |
#define HCI_RX_BUF_QUEUE_SIZE 4 |
#define HCI_RX_BUF_SIZE 600 |
#define HCI_SLIP_ENABLED 0 |
#define HCI_TRANSPORT_ENABLED 0 |
#define HCI_TX_BUF_SIZE 600 |
#define HCI_UART_BAUDRATE 30801920 |
#define HCI_UART_CTS_PIN 7 |
#define HCI_UART_FLOW_CONTROL 0 |
#define HCI_UART_RTS_PIN 5 |
#define HCI_UART_RX_PIN 8 |
#define HCI_UART_TX_PIN 6 |
#define I2S_CONFIG_ALIGN 0 |
#define I2S_CONFIG_CHANNELS 1 |
#define I2S_CONFIG_DEBUG_COLOR 0 |
#define I2S_CONFIG_FORMAT 0 |
#define I2S_CONFIG_INFO_COLOR 0 |
#define I2S_CONFIG_IRQ_PRIORITY 6 |
#define I2S_CONFIG_LOG_ENABLED 0 |
#define I2S_CONFIG_LOG_LEVEL 3 |
#define I2S_CONFIG_LRCK_PIN 30 |
#define I2S_CONFIG_MASTER 0 |
#define I2S_CONFIG_MCK_PIN 255 |
#define I2S_CONFIG_MCK_SETUP 536870912 |
#define I2S_CONFIG_RATIO 2000 |
#define I2S_CONFIG_SCK_PIN 31 |
#define I2S_CONFIG_SDIN_PIN 28 |
#define I2S_CONFIG_SDOUT_PIN 29 |
#define I2S_CONFIG_SWIDTH 1 |
#define I2S_ENABLED 0 |
#define LED_SOFTBLINK_ENABLED 0 |
#define LOW_POWER_PWM_ENABLED 0 |
#define LPCOMP_CONFIG_DEBUG_COLOR 0 |
#define LPCOMP_CONFIG_DETECTION 2 |
#define LPCOMP_CONFIG_HYST 0 |
#define LPCOMP_CONFIG_INFO_COLOR 0 |
#define LPCOMP_CONFIG_INPUT 0 |
#define LPCOMP_CONFIG_IRQ_PRIORITY 6 |
#define LPCOMP_CONFIG_LOG_ENABLED 0 |
#define LPCOMP_CONFIG_LOG_LEVEL 3 |
#define LPCOMP_CONFIG_REFERENCE 3 |
#define LPCOMP_ENABLED 0 |
#define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0 |
#define MAX3421E_HOST_CONFIG_INFO_COLOR 0 |
#define MAX3421E_HOST_CONFIG_LOG_ENABLED 0 |
#define MAX3421E_HOST_CONFIG_LOG_LEVEL 3 |
#define MEASUREMENT_PERIOD 20 |
#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0 |
#define MEM_MANAGER_CONFIG_INFO_COLOR 0 |
#define MEM_MANAGER_CONFIG_LOG_ENABLED 0 |
#define MEM_MANAGER_CONFIG_LOG_LEVEL 3 |
#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 |
#define MEM_MANAGER_ENABLED 0 |
#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 |
#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 |
#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 |
#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 |
#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 |
#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 |
#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0 |
#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320 |
#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0 |
#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64 |
#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0 |
#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444 |
#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0 |
#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32 |
#define NFC_AC_REC_ENABLED 0 |
#define NFC_AC_REC_PARSER_ENABLED 0 |
#define NFC_BLE_OOB_ADVDATA_ENABLED 0 |
#define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0 |
#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 |
#define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0 |
#define NFC_BLE_PAIR_LIB_ENABLED 0 |
#define NFC_BLE_PAIR_LIB_INFO_COLOR 0 |
#define NFC_BLE_PAIR_LIB_LOG_ENABLED 0 |
#define NFC_BLE_PAIR_LIB_LOG_LEVEL 3 |
#define NFC_BLE_PAIR_MSG_ENABLED 0 |
#define NFC_CH_COMMON_ENABLED 0 |
#define NFC_EP_OOB_REC_ENABLED 0 |
#define NFC_HS_REC_ENABLED 0 |
#define NFC_LE_OOB_REC_ENABLED 0 |
#define NFC_LE_OOB_REC_PARSER_ENABLED 0 |
#define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0 |
#define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0 |
#define NFC_NDEF_MSG_ENABLED 0 |
#define NFC_NDEF_MSG_PARSER_ENABLED 0 |
#define NFC_NDEF_MSG_PARSER_INFO_COLOR 0 |
#define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0 |
#define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3 |
#define NFC_NDEF_MSG_TAG_TYPE 2 |
#define NFC_NDEF_RECORD_ENABLED 0 |
#define NFC_NDEF_RECORD_PARSER_ENABLED 0 |
#define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0 |
#define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0 |
#define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3 |
#define NFC_NDEF_TEXT_RECORD_ENABLED 0 |
#define NFC_NDEF_URI_MSG_ENABLED 0 |
#define NFC_NDEF_URI_REC_ENABLED 0 |
#define NFC_PLATFORM_DEBUG_COLOR 0 |
#define NFC_PLATFORM_ENABLED 0 |
#define NFC_PLATFORM_INFO_COLOR 0 |
#define NFC_PLATFORM_LOG_ENABLED 0 |
#define NFC_PLATFORM_LOG_LEVEL 3 |
#define NFC_T2T_PARSER_ENABLED 0 |
#define NFC_T2T_PARSER_INFO_COLOR 0 |
#define NFC_T2T_PARSER_LOG_ENABLED 0 |
#define NFC_T2T_PARSER_LOG_LEVEL 3 |
#define NFC_T4T_APDU_ENABLED 0 |
#define NFC_T4T_APDU_LOG_COLOR 0 |
#define NFC_T4T_APDU_LOG_ENABLED 0 |
#define NFC_T4T_APDU_LOG_LEVEL 3 |
#define NFC_T4T_CC_FILE_PARSER_ENABLED 0 |
#define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0 |
#define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0 |
#define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3 |
#define NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED 0 |
#define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0 |
#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0 |
#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3 |
#define NFC_T4T_TLV_BLOCK_PARSER_ENABLED 0 |
#define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0 |
#define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0 |
#define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3 |
#define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0 |
#define NRF_ATFIFO_CONFIG_INFO_COLOR 0 |
#define NRF_ATFIFO_CONFIG_LOG_ENABLED 1 |
#define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3 |
#define NRF_ATFIFO_CONFIG_LOG_LEVEL 3 |
#define NRF_BALLOC_CLI_CMDS 0 |
#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0 |
#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0 |
#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0 |
#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0 |
#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0 |
#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1 |
#define NRF_BALLOC_CONFIG_INFO_COLOR 0 |
#define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3 |
#define NRF_BALLOC_CONFIG_LOG_ENABLED 0 |
#define NRF_BALLOC_CONFIG_LOG_LEVEL 3 |
#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1 |
#define NRF_BALLOC_ENABLED 1 |
#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2 |
#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2 |
#define NRF_BLE_CONN_PARAMS_ENABLED 1 |
#define NRF_BLE_CONN_PARAMS_MAX_SLAVE_LATENCY_DEVIATION 499 |
#define NRF_BLE_CONN_PARAMS_MAX_SUPERVISION_TIMEOUT_DEVIATION 65535 |
#define NRF_BLE_ES_BLE_OBSERVER_PRIO 2 |
#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 3 |
#define NRF_BLE_GATT_ENABLED 1 |
#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2 |
#define NRF_BLE_GQ_BLE_OBSERVER_PRIO 1 |
#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 3 |
#define NRF_BLE_QWR_ENABLED 1 |
#define NRF_BLE_QWR_MAX_ATTR 6 |
#define NRF_BLE_SCAN_OBSERVER_PRIO 1 |
#define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0 |
#define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0 |
#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0 |
#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3 |
#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3 |
#define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0 |
#define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0 |
#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0 |
#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3 |
#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3 |
#define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0 |
#define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0 |
#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0 |
#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3 |
#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3 |
#define NRF_CLI_ARGC_MAX 12 |
#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0 |
#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0 |
#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0 |
#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3 |
#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1 |
#define NRF_CLI_CMD_BUFF_SIZE 128 |
#define NRF_CLI_ECHO_STATUS 1 |
#define NRF_CLI_ENABLED 0 |
#define NRF_CLI_HISTORY_ELEMENT_COUNT 8 |
#define NRF_CLI_HISTORY_ELEMENT_SIZE 32 |
#define NRF_CLI_HISTORY_ENABLED 1 |
#define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0 |
#define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0 |
#define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0 |
#define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3 |
#define NRF_CLI_LOG_BACKEND 1 |
#define NRF_CLI_METAKEYS_ENABLED 0 |
#define NRF_CLI_PRINTF_BUFF_SIZE 23 |
#define NRF_CLI_STATISTICS_ENABLED 1 |
#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0 |
#define NRF_CLI_UART_CONFIG_INFO_COLOR 0 |
#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0 |
#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3 |
#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0 |
#define NRF_CLI_VT100_COLORS_ENABLED 1 |
#define NRF_CLI_WILDCARD_ENABLED 0 |
#define NRF_CLOCK_ENABLED 1 |
#define NRF_CRYPTO_ALLOCATOR 0 |
#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096 |
#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED 1 |
#define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0 |
#define NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED 0 |
#define NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED 0 |
#define NRF_CRYPTO_ENABLED 1 |
#define NRF_CSENSE_ENABLED 0 |
#define NRF_CSENSE_MAX_PADS_NUMBER 20 |
#define NRF_CSENSE_MAX_VALUE 1000 |
#define NRF_CSENSE_MIN_PAD_VALUE 20 |
#define NRF_CSENSE_OUTPUT_PIN 26 |
#define NRF_CSENSE_PAD_DEVIATION 70 |
#define NRF_CSENSE_PAD_HYSTERESIS 15 |
#define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0 |
#define NRF_DRV_CSENSE_ENABLED 0 |
#define NRF_FPRINTF_DOUBLE_ENABLED 0 |
#define NRF_FPRINTF_ENABLED 1 |
#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1 |
#define NRF_FSTORAGE_ENABLED 1 |
#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0 |
#define NRF_FSTORAGE_SD_MAX_RETRIES 8 |
#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096 |
#define NRF_FSTORAGE_SD_QUEUE_SIZE 4 |
#define NRF_GFX_ENABLED 0 |
#define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0 |
#define NRF_LIBUARTE_CONFIG_INFO_COLOR 0 |
#define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0 |
#define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3 |
#define NRF_LOG_ALLOW_OVERFLOW 1 |
#define NRF_LOG_BACKEND_RTT_ENABLED 1 |
#define NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE 64 |
#define NRF_LOG_BACKEND_RTT_TX_RETRY_CNT 3 |
#define NRF_LOG_BACKEND_RTT_TX_RETRY_DELAY_MS 1 |
#define NRF_LOG_BACKEND_UART_BAUDRATE 30801920 |
#define NRF_LOG_BACKEND_UART_ENABLED 0 |
#define NRF_LOG_BACKEND_UART_TEMP_BUFFER_SIZE 64 |
#define NRF_LOG_BACKEND_UART_TX_PIN 6 |
#define NRF_LOG_BUFSIZE 1024 |
#define NRF_LOG_CLI_CMDS 1 |
#define NRF_LOG_COLOR_DEFAULT 0 |
#define NRF_LOG_DEFAULT_LEVEL 4 |
#define NRF_LOG_DEFERRED 0 |
#define NRF_LOG_ENABLED 1 |
#define NRF_LOG_ERROR_COLOR 2 |
#define NRF_LOG_FILTERS_ENABLED 0 |
#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8 |
#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20 |
#define NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED 0 |
#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1 |
#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128 |
#define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0 |
#define NRF_LOG_USES_COLORS 1 |
#define NRF_LOG_USES_TIMESTAMP 0 |
#define NRF_LOG_WARNING_COLOR 4 |
#define NRF_MAXIMUM_LATENCY_US 2000 |
#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0 |
#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0 |
#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0 |
#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3 |
#define NRF_MEMOBJ_ENABLED 1 |
#define NRF_MPU_LIB_CLI_CMDS 0 |
#define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0 |
#define NRF_MPU_LIB_CONFIG_INFO_COLOR 0 |
#define NRF_MPU_LIB_CONFIG_LOG_ENABLED 1 |
#define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3 |
#define NRF_MPU_LIB_ENABLED 0 |
#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 1 |
#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0 |
#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0 |
#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0 |
#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 1 |
#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3 |
#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0 |
#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0 |
#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3 |
#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0 |
#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3 |
#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0 |
#define NRF_PWR_MGMT_ENABLED 1 |
#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31 |
#define NRF_QUEUE_CLI_CMDS 0 |
#define NRF_QUEUE_CONFIG_DEBUG_COLOR 0 |
#define NRF_QUEUE_CONFIG_INFO_COLOR 0 |
#define NRF_QUEUE_CONFIG_LOG_ENABLED 0 |
#define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3 |
#define NRF_QUEUE_CONFIG_LOG_LEVEL 3 |
#define NRF_QUEUE_ENABLED 0 |
#define NRF_SDH_ANT_DEBUG_COLOR 0 |
#define NRF_SDH_ANT_INFO_COLOR 0 |
#define NRF_SDH_ANT_LOG_ENABLED 0 |
#define NRF_SDH_ANT_LOG_LEVEL 3 |
#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0 |
#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0 |
#define NRF_SDH_BLE_DEBUG_COLOR 0 |
#define NRF_SDH_BLE_ENABLED 1 |
#define NRF_SDH_BLE_GAP_DATA_LENGTH 101 |
#define NRF_SDH_BLE_GAP_EVENT_LENGTH 40 |
#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 104 |
#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408 |
#define NRF_SDH_BLE_INFO_COLOR 0 |
#define NRF_SDH_BLE_LOG_ENABLED 1 |
#define NRF_SDH_BLE_LOG_LEVEL 4 |
#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 4 |
#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 1 |
#define NRF_SDH_BLE_SERVICE_CHANGED 1 |
#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0 |
#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1 |
#define NRF_SDH_BLE_VS_UUID_COUNT 1 |
#define NRF_SDH_CLOCK_LF_ACCURACY 7 |
#define NRF_SDH_CLOCK_LF_RC_CTIV 16 |
#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 2 |
#define NRF_SDH_CLOCK_LF_SRC 0 |
#define NRF_SDH_DEBUG_COLOR 0 |
#define NRF_SDH_DISPATCH_MODEL 0 |
#define NRF_SDH_ENABLED 1 |
#define NRF_SDH_INFO_COLOR 0 |
#define NRF_SDH_LOG_ENABLED 1 |
#define NRF_SDH_LOG_LEVEL 4 |
#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2 |
#define NRF_SDH_SOC_DEBUG_COLOR 0 |
#define NRF_SDH_SOC_ENABLED 1 |
#define NRF_SDH_SOC_INFO_COLOR 0 |
#define NRF_SDH_SOC_LOG_ENABLED 1 |
#define NRF_SDH_SOC_LOG_LEVEL 3 |
#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2 |
#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0 |
#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2 |
#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2 |
#define NRF_SECTION_ITER_ENABLED 1 |
#define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0 |
#define NRF_SORTLIST_CONFIG_INFO_COLOR 0 |
#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0 |
#define NRF_SORTLIST_CONFIG_LOG_LEVEL 3 |
#define NRF_SORTLIST_ENABLED 1 |
#define NRF_SPI_DRV_MISO_PULLUP_CFG 3 |
#define NRF_SPI_MNGR_ENABLED 0 |
#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0 |
#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0 |
#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0 |
#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3 |
#define NRF_STACK_GUARD_CONFIG_SIZE 7 |
#define NRF_STACK_GUARD_ENABLED 0 |
#define NRF_STRERROR_ENABLED 1 |
#define NRF_TWI_MNGR_ENABLED 1 |
#define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0 |
#define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0 |
#define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0 |
#define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3 |
#define NRF_TWI_SENSOR_ENABLED 0 |
#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 |
#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 |
#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_CLOCK_CONFIG_LF_SRC 0 |
#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 |
#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 |
#define NRFX_CLOCK_ENABLED 1 |
#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 |
#define NRFX_COMP_CONFIG_HYST 0 |
#define NRFX_COMP_CONFIG_INFO_COLOR 0 |
#define NRFX_COMP_CONFIG_INPUT 0 |
#define NRFX_COMP_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_COMP_CONFIG_ISOURCE 0 |
#define NRFX_COMP_CONFIG_LOG_ENABLED 0 |
#define NRFX_COMP_CONFIG_LOG_LEVEL 3 |
#define NRFX_COMP_CONFIG_MAIN_MODE 0 |
#define NRFX_COMP_CONFIG_REF 1 |
#define NRFX_COMP_CONFIG_SPEED_MODE 2 |
#define NRFX_COMP_ENABLED 0 |
#define NRFX_EGU_ENABLED 0 |
#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 |
#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 |
#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7 |
#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 |
#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 |
#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 |
#define NRFX_GPIOTE_ENABLED 1 |
#define NRFX_I2S_CONFIG_ALIGN 0 |
#define NRFX_I2S_CONFIG_CHANNELS 1 |
#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 |
#define NRFX_I2S_CONFIG_FORMAT 0 |
#define NRFX_I2S_CONFIG_INFO_COLOR 0 |
#define NRFX_I2S_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_I2S_CONFIG_LOG_ENABLED 0 |
#define NRFX_I2S_CONFIG_LOG_LEVEL 3 |
#define NRFX_I2S_CONFIG_LRCK_PIN 30 |
#define NRFX_I2S_CONFIG_MASTER 0 |
#define NRFX_I2S_CONFIG_MCK_PIN 255 |
#define NRFX_I2S_CONFIG_MCK_SETUP 536870912 |
#define NRFX_I2S_CONFIG_RATIO 2000 |
#define NRFX_I2S_CONFIG_SCK_PIN 31 |
#define NRFX_I2S_CONFIG_SDIN_PIN 28 |
#define NRFX_I2S_CONFIG_SDOUT_PIN 29 |
#define NRFX_I2S_CONFIG_SWIDTH 1 |
#define NRFX_I2S_ENABLED 0 |
#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0 |
#define NRFX_LPCOMP_CONFIG_DETECTION 2 |
#define NRFX_LPCOMP_CONFIG_HYST 0 |
#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0 |
#define NRFX_LPCOMP_CONFIG_INPUT 0 |
#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 |
#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 |
#define NRFX_LPCOMP_CONFIG_REFERENCE 3 |
#define NRFX_LPCOMP_ENABLED 0 |
#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0 |
#define NRFX_NFCT_CONFIG_INFO_COLOR 0 |
#define NRFX_NFCT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 |
#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 |
#define NRFX_NFCT_ENABLED 0 |
#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032 |
#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 |
#define NRFX_PDM_CONFIG_EDGE 0 |
#define NRFX_PDM_CONFIG_INFO_COLOR 0 |
#define NRFX_PDM_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_PDM_CONFIG_LOG_ENABLED 0 |
#define NRFX_PDM_CONFIG_LOG_LEVEL 3 |
#define NRFX_PDM_CONFIG_MODE 1 |
#define NRFX_PDM_ENABLED 0 |
#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 |
#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 |
#define NRFX_POWER_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_POWER_ENABLED 0 |
#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 |
#define NRFX_PPI_CONFIG_INFO_COLOR 0 |
#define NRFX_PPI_CONFIG_LOG_ENABLED 0 |
#define NRFX_PPI_CONFIG_LOG_LEVEL 3 |
#define NRFX_PPI_ENABLED 0 |
#define NRFX_PRS_BOX_0_ENABLED 0 |
#define NRFX_PRS_BOX_1_ENABLED 0 |
#define NRFX_PRS_BOX_2_ENABLED 0 |
#define NRFX_PRS_BOX_3_ENABLED 0 |
#define NRFX_PRS_BOX_4_ENABLED 1 |
#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 |
#define NRFX_PRS_CONFIG_INFO_COLOR 0 |
#define NRFX_PRS_CONFIG_LOG_ENABLED 0 |
#define NRFX_PRS_CONFIG_LOG_LEVEL 3 |
#define NRFX_PRS_ENABLED 1 |
#define NRFX_PWM0_ENABLED 0 |
#define NRFX_PWM1_ENABLED 0 |
#define NRFX_PWM2_ENABLED 0 |
#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 |
#define NRFX_PWM_CONFIG_INFO_COLOR 0 |
#define NRFX_PWM_CONFIG_LOG_ENABLED 0 |
#define NRFX_PWM_CONFIG_LOG_LEVEL 3 |
#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4 |
#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0 |
#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0 |
#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31 |
#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31 |
#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31 |
#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31 |
#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0 |
#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000 |
#define NRFX_PWM_ENABLED 1 |
#define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE 5 |
#define NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 |
#define NRFX_QDEC_CONFIG_DBFEN 0 |
#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 |
#define NRFX_QDEC_CONFIG_INFO_COLOR 0 |
#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_QDEC_CONFIG_LEDPOL 1 |
#define NRFX_QDEC_CONFIG_LEDPRE 511 |
#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 |
#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 |
#define NRFX_QDEC_CONFIG_PIO_A 31 |
#define NRFX_QDEC_CONFIG_PIO_B 31 |
#define NRFX_QDEC_CONFIG_PIO_LED 31 |
#define NRFX_QDEC_CONFIG_REPORTPER 0 |
#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 |
#define NRFX_QDEC_CONFIG_SAMPLEPER 7 |
#define NRFX_QDEC_ENABLED 0 |
#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 |
#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 |
#define NRFX_RNG_CONFIG_INFO_COLOR 0 |
#define NRFX_RNG_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_RNG_CONFIG_LOG_ENABLED 0 |
#define NRFX_RNG_CONFIG_LOG_LEVEL 3 |
#define NRFX_RNG_ENABLED 0 |
#define NRFX_RTC0_ENABLED 0 |
#define NRFX_RTC1_ENABLED 0 |
#define NRFX_RTC2_ENABLED 0 |
#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 |
#define NRFX_RTC_CONFIG_INFO_COLOR 0 |
#define NRFX_RTC_CONFIG_LOG_ENABLED 0 |
#define NRFX_RTC_CONFIG_LOG_LEVEL 3 |
#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 |
#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 |
#define NRFX_RTC_ENABLED 0 |
#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 |
#define NRFX_SAADC_CONFIG_DEBUG_COLOR 3 |
#define NRFX_SAADC_CONFIG_INFO_COLOR 0 |
#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_SAADC_CONFIG_LOG_ENABLED 1 |
#define NRFX_SAADC_CONFIG_LOG_LEVEL 1 |
#define NRFX_SAADC_CONFIG_LP_MODE 0 |
#define NRFX_SAADC_CONFIG_OVERSAMPLE 6 |
#define NRFX_SAADC_CONFIG_RESOLUTION 3 |
#define NRFX_SAADC_ENABLED 1 |
#define NRFX_SPI0_ENABLED 0 |
#define NRFX_SPI1_ENABLED 0 |
#define NRFX_SPI2_ENABLED 0 |
#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 |
#define NRFX_SPI_CONFIG_INFO_COLOR 0 |
#define NRFX_SPI_CONFIG_LOG_ENABLED 0 |
#define NRFX_SPI_CONFIG_LOG_LEVEL 3 |
#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_SPI_ENABLED 0 |
#define NRFX_SPI_MISO_PULL_CFG 1 |
#define NRFX_SPIM0_ENABLED 1 |
#define NRFX_SPIM1_ENABLED 1 |
#define NRFX_SPIM2_ENABLED 0 |
#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 |
#define NRFX_SPIM_CONFIG_INFO_COLOR 0 |
#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 |
#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 |
#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_SPIM_ENABLED 1 |
#define NRFX_SPIM_MISO_PULL_CFG 3 |
#define NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 |
#define NRFX_SPIS0_ENABLED 0 |
#define NRFX_SPIS1_ENABLED 0 |
#define NRFX_SPIS2_ENABLED 0 |
#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 |
#define NRFX_SPIS_CONFIG_INFO_COLOR 0 |
#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 |
#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 |
#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_SPIS_DEFAULT_DEF 255 |
#define NRFX_SPIS_DEFAULT_ORC 255 |
#define NRFX_SPIS_ENABLED 0 |
#define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 |
#define NRFX_SWI0_DISABLED 0 |
#define NRFX_SWI1_DISABLED 0 |
#define NRFX_SWI2_DISABLED 0 |
#define NRFX_SWI3_DISABLED 0 |
#define NRFX_SWI4_DISABLED 0 |
#define NRFX_SWI5_DISABLED 0 |
#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 |
#define NRFX_SWI_CONFIG_INFO_COLOR 0 |
#define NRFX_SWI_CONFIG_LOG_ENABLED 0 |
#define NRFX_SWI_CONFIG_LOG_LEVEL 3 |
#define NRFX_SWI_ENABLED 0 |
#define NRFX_SYSTICK_ENABLED 1 |
#define NRFX_TIMER0_ENABLED 1 |
#define NRFX_TIMER1_ENABLED 1 |
#define NRFX_TIMER2_ENABLED 2 |
#define NRFX_TIMER3_ENABLED 0 |
#define NRFX_TIMER4_ENABLED 0 |
#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 |
#define NRFX_TIMER_CONFIG_INFO_COLOR 0 |
#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 |
#define NRFX_TIMER_CONFIG_LOG_LEVEL 4 |
#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 |
#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 |
#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 |
#define NRFX_TIMER_ENABLED 1 |
#define NRFX_TWI0_ENABLED 1 |
#define NRFX_TWI1_ENABLED 0 |
#define NRFX_TWI_CONFIG_DEBUG_COLOR 3 |
#define NRFX_TWI_CONFIG_INFO_COLOR 0 |
#define NRFX_TWI_CONFIG_LOG_ENABLED 1 |
#define NRFX_TWI_CONFIG_LOG_LEVEL 4 |
#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 |
#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 |
#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_TWI_ENABLED 1 |
#define NRFX_TWIM0_ENABLED 1 |
#define NRFX_TWIM1_ENABLED 0 |
#define NRFX_TWIM_CONFIG_DEBUG_COLOR 3 |
#define NRFX_TWIM_CONFIG_INFO_COLOR 0 |
#define NRFX_TWIM_CONFIG_LOG_ENABLED 1 |
#define NRFX_TWIM_CONFIG_LOG_LEVEL 4 |
#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 104857600 |
#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 |
#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_TWIM_ENABLED 1 |
#define NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1 |
#define NRFX_TWIS0_ENABLED 0 |
#define NRFX_TWIS1_ENABLED 0 |
#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 |
#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 |
#define NRFX_TWIS_CONFIG_INFO_COLOR 0 |
#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 |
#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 |
#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 |
#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 |
#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 |
#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 |
#define NRFX_TWIS_ENABLED 0 |
#define NRFX_TWIS_NO_SYNC_MODE 0 |
#define NRFX_UART0_ENABLED 0 |
#define NRFX_UART_CONFIG_DEBUG_COLOR 0 |
#define NRFX_UART_CONFIG_INFO_COLOR 3 |
#define NRFX_UART_CONFIG_LOG_ENABLED 1 |
#define NRFX_UART_CONFIG_LOG_LEVEL 4 |
#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 |
#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 |
#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 |
#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 |
#define NRFX_UART_ENABLED 0 |
#define NRFX_UARTE0_ENABLED 1 |
#define NRFX_UARTE_CONFIG_DEBUG_COLOR 3 |
#define NRFX_UARTE_CONFIG_INFO_COLOR 0 |
#define NRFX_UARTE_CONFIG_LOG_ENABLED 1 |
#define NRFX_UARTE_CONFIG_LOG_LEVEL 4 |
#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 2576384 |
#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 |
#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 |
#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 |
#define NRFX_UARTE_ENABLED 1 |
#define NRFX_USBD_CONFIG_DEBUG_COLOR 0 |
#define NRFX_USBD_CONFIG_INFO_COLOR 0 |
#define NRFX_USBD_CONFIG_LOG_ENABLED 0 |
#define NRFX_USBD_CONFIG_LOG_LEVEL 3 |
#define NRFX_WDT_CONFIG_BEHAVIOUR 1 |
#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 |
#define NRFX_WDT_CONFIG_INFO_COLOR 0 |
#define NRFX_WDT_CONFIG_IRQ_PRIORITY 6 |
#define NRFX_WDT_CONFIG_LOG_ENABLED 0 |
#define NRFX_WDT_CONFIG_LOG_LEVEL 3 |
#define NRFX_WDT_CONFIG_NO_IRQ 0 |
#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 |
#define NRFX_WDT_ENABLED 0 |
#define PDM_CONFIG_CLOCK_FREQ 138412032 |
#define PDM_CONFIG_DEBUG_COLOR 0 |
#define PDM_CONFIG_EDGE 0 |
#define PDM_CONFIG_INFO_COLOR 0 |
#define PDM_CONFIG_IRQ_PRIORITY 6 |
#define PDM_CONFIG_LOG_ENABLED 0 |
#define PDM_CONFIG_LOG_LEVEL 3 |
#define PDM_CONFIG_MODE 1 |
#define PDM_ENABLED 0 |
#define PEER_MANAGER_ENABLED 1 |
#define PM_BLE_OBSERVER_PRIO 1 |
#define PM_CENTRAL_ENABLED 0 |
#define PM_FLASH_BUFFERS 4 |
#define PM_HANDLER_SEC_DELAY_MS 0 |
#define PM_LESC_ENABLED 0 |
#define PM_LOG_DEBUG_COLOR 0 |
#define PM_LOG_ENABLED 1 |
#define PM_LOG_INFO_COLOR 0 |
#define PM_LOG_LEVEL 3 |
#define PM_MAX_REGISTRANTS 3 |
#define PM_PEER_RANKS_ENABLED 1 |
#define PM_RA_PROTECTION_ENABLED 0 |
#define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000 |
#define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000 |
#define PM_RA_PROTECTION_REWARD_PERIOD 10000 |
#define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8 |
#define PM_SERVICE_CHANGED_ENABLED 1 |
#define POWER_CONFIG_DEFAULT_DCDCEN 0 |
#define POWER_CONFIG_DEFAULT_DCDCENHV 0 |
#define POWER_CONFIG_IRQ_PRIORITY 6 |
#define POWER_CONFIG_SOC_OBSERVER_PRIO 0 |
#define POWER_CONFIG_STATE_OBSERVER_PRIO 0 |
#define POWER_ENABLED 0 |
#define PPI_CONFIG_DEBUG_COLOR 0 |
#define PPI_CONFIG_INFO_COLOR 0 |
#define PPI_CONFIG_LOG_ENABLED 0 |
#define PPI_CONFIG_LOG_LEVEL 3 |
#define PPI_ENABLED 0 |
#define PWM0_ENABLED 1 |
#define PWM1_ENABLED 1 |
#define PWM2_ENABLED 1 |
#define PWM_CONFIG_DEBUG_COLOR 0 |
#define PWM_CONFIG_INFO_COLOR 0 |
#define PWM_CONFIG_LOG_ENABLED 0 |
#define PWM_CONFIG_LOG_LEVEL 3 |
#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 |
#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 |
#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 |
#define PWM_DEFAULT_CONFIG_OUT0_PIN 31 |
#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 |
#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 |
#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 |
#define PWM_DEFAULT_CONFIG_STEP_MODE 0 |
#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 |
#define PWM_ENABLED 1 |
#define PWM_NRF52_ANOMALY_109_EGU_INSTANCE 5 |
#define PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 |
#define QDEC_CONFIG_DBFEN 0 |
#define QDEC_CONFIG_DEBUG_COLOR 0 |
#define QDEC_CONFIG_INFO_COLOR 0 |
#define QDEC_CONFIG_IRQ_PRIORITY 6 |
#define QDEC_CONFIG_LEDPOL 1 |
#define QDEC_CONFIG_LEDPRE 511 |
#define QDEC_CONFIG_LOG_ENABLED 0 |
#define QDEC_CONFIG_LOG_LEVEL 3 |
#define QDEC_CONFIG_PIO_A 31 |
#define QDEC_CONFIG_PIO_B 31 |
#define QDEC_CONFIG_PIO_LED 31 |
#define QDEC_CONFIG_REPORTPER 0 |
#define QDEC_CONFIG_SAMPLE_INTEN 0 |
#define QDEC_CONFIG_SAMPLEPER 7 |
#define QDEC_ENABLED 0 |
#define QSPI_CONFIG_ADDRMODE 0 |
#define QSPI_CONFIG_FREQUENCY 15 |
#define QSPI_CONFIG_IRQ_PRIORITY 6 |
#define QSPI_CONFIG_MODE 0 |
#define QSPI_CONFIG_READOC 0 |
#define QSPI_CONFIG_SCK_DELAY 1 |
#define QSPI_CONFIG_WRITEOC 0 |
#define QSPI_CONFIG_XIP_OFFSET 0 |
#define QSPI_ENABLED 0 |
#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED |
#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED |
#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED |
#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED |
#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED |
#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED |
#define RNG_CONFIG_DEBUG_COLOR 0 |
#define RNG_CONFIG_ERROR_CORRECTION 1 |
#define RNG_CONFIG_INFO_COLOR 0 |
#define RNG_CONFIG_IRQ_PRIORITY 6 |
#define RNG_CONFIG_LOG_ENABLED 0 |
#define RNG_CONFIG_LOG_LEVEL 3 |
#define RNG_CONFIG_POOL_SIZE 64 |
#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0 |
#define RNG_CONFIG_STATE_OBSERVER_PRIO 0 |
#define RNG_ENABLED 0 |
#define RTC0_ENABLED 0 |
#define RTC1_ENABLED 0 |
#define RTC2_ENABLED 0 |
#define RTC_CONFIG_DEBUG_COLOR 0 |
#define RTC_CONFIG_INFO_COLOR 0 |
#define RTC_CONFIG_LOG_ENABLED 0 |
#define RTC_CONFIG_LOG_LEVEL 3 |
#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 |
#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define RTC_DEFAULT_CONFIG_RELIABLE 0 |
#define RTC_ENABLED 0 |
#define SAADC_CONFIG_DEBUG_COLOR 0 |
#define SAADC_CONFIG_INFO_COLOR 0 |
#define SAADC_CONFIG_IRQ_PRIORITY 6 |
#define SAADC_CONFIG_LOG_ENABLED 1 |
#define SAADC_CONFIG_LOG_LEVEL 1 |
#define SAADC_CONFIG_LP_MODE 1 |
#define SAADC_CONFIG_OVERSAMPLE 8 |
#define SAADC_CONFIG_RESOLUTION 3 |
#define SAADC_ENABLED 1 |
#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16 |
#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 512 |
#define SEGGER_RTT_CONFIG_DEFAULT_MODE 0 |
#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 2 |
#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 2 |
#define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0 |
#define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0 |
#define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0 |
#define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3 |
#define SLIP_ENABLED 0 |
#define SPI0_ENABLED 0 |
#define SPI0_USE_EASY_DMA 1 |
#define SPI1_ENABLED 1 |
#define SPI1_USE_EASY_DMA 1 |
#define SPI2_ENABLED 0 |
#define SPI2_USE_EASY_DMA 1 |
#define SPI_CONFIG_DEBUG_COLOR 0 |
#define SPI_CONFIG_INFO_COLOR 0 |
#define SPI_CONFIG_LOG_ENABLED 0 |
#define SPI_CONFIG_LOG_LEVEL 3 |
#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define SPI_ENABLED 1 |
#define SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 |
#define SPIS0_ENABLED 0 |
#define SPIS1_ENABLED 0 |
#define SPIS2_ENABLED 0 |
#define SPIS_CONFIG_DEBUG_COLOR 0 |
#define SPIS_CONFIG_INFO_COLOR 0 |
#define SPIS_CONFIG_LOG_ENABLED 0 |
#define SPIS_CONFIG_LOG_LEVEL 3 |
#define SPIS_DEFAULT_BIT_ORDER 0 |
#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define SPIS_DEFAULT_DEF 255 |
#define SPIS_DEFAULT_MODE 0 |
#define SPIS_DEFAULT_ORC 255 |
#define SPIS_ENABLED 0 |
#define SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 |
#define TASK_MANAGER_CLI_CMDS 0 |
#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0 |
#define TASK_MANAGER_CONFIG_INFO_COLOR 0 |
#define TASK_MANAGER_CONFIG_LOG_ENABLED 0 |
#define TASK_MANAGER_CONFIG_LOG_LEVEL 3 |
#define TASK_MANAGER_CONFIG_MAX_TASKS 2 |
#define TASK_MANAGER_CONFIG_STACK_GUARD 7 |
#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1 |
#define TASK_MANAGER_CONFIG_STACK_SIZE 1024 |
#define TASK_MANAGER_ENABLED 0 |
#define TIMER0_ENABLED 1 |
#define TIMER0_FOR_CSENSE 1 |
#define TIMER1_ENABLED 1 |
#define TIMER1_FOR_CSENSE 2 |
#define TIMER2_ENABLED 1 |
#define TIMER3_ENABLED 0 |
#define TIMER4_ENABLED 0 |
#define TIMER_CONFIG_DEBUG_COLOR 0 |
#define TIMER_CONFIG_INFO_COLOR 0 |
#define TIMER_CONFIG_LOG_ENABLED 0 |
#define TIMER_CONFIG_LOG_LEVEL 3 |
#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 |
#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 |
#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define TIMER_DEFAULT_CONFIG_MODE 0 |
#define TIMER_ENABLED 1 |
#define TWI0_ENABLED 1 |
#define TWI0_USE_EASY_DMA 1 |
#define TWI1_ENABLED 0 |
#define TWI1_USE_EASY_DMA 0 |
#define TWI_CONFIG_DEBUG_COLOR 0 |
#define TWI_CONFIG_INFO_COLOR 0 |
#define TWI_CONFIG_LOG_ENABLED 0 |
#define TWI_CONFIG_LOG_LEVEL 3 |
#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 |
#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 |
#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 |
#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define TWI_ENABLED 1 |
#define TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1 |
#define TWIS0_ENABLED 0 |
#define TWIS1_ENABLED 0 |
#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 |
#define TWIS_CONFIG_DEBUG_COLOR 0 |
#define TWIS_CONFIG_INFO_COLOR 0 |
#define TWIS_CONFIG_LOG_ENABLED 0 |
#define TWIS_CONFIG_LOG_LEVEL 3 |
#define TWIS_DEFAULT_CONFIG_ADDR0 0 |
#define TWIS_DEFAULT_CONFIG_ADDR1 0 |
#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 |
#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 |
#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 |
#define TWIS_ENABLED 0 |
#define TWIS_NO_SYNC_MODE 0 |
#define UART0_CONFIG_USE_EASY_DMA 1 |
#define UART0_ENABLED 1 |
#define UART_CONFIG_DEBUG_COLOR 0 |
#define UART_CONFIG_INFO_COLOR 0 |
#define UART_CONFIG_LOG_ENABLED 0 |
#define UART_CONFIG_LOG_LEVEL 3 |
#define UART_DEFAULT_CONFIG_BAUDRATE 30801920 |
#define UART_DEFAULT_CONFIG_HWFC 0 |
#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 |
#define UART_DEFAULT_CONFIG_PARITY 0 |
#define UART_EASY_DMA_SUPPORT 1 |
#define UART_ENABLED 1 |
#define UART_LEGACY_SUPPORT 1 |
#define USBD_CONFIG_DEBUG_COLOR 0 |
#define USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 |
#define USBD_CONFIG_DMASCHEDULER_MODE 0 |
#define USBD_CONFIG_INFO_COLOR 0 |
#define USBD_CONFIG_IRQ_PRIORITY 6 |
#define USBD_CONFIG_ISO_IN_ZLP 0 |
#define USBD_CONFIG_LOG_ENABLED 0 |
#define USBD_CONFIG_LOG_LEVEL 3 |
#define USBD_ENABLED 0 |
#define USE_COMP 0 |
#define WDT_CONFIG_BEHAVIOUR 1 |
#define WDT_CONFIG_DEBUG_COLOR 0 |
#define WDT_CONFIG_INFO_COLOR 0 |
#define WDT_CONFIG_IRQ_PRIORITY 6 |
#define WDT_CONFIG_LOG_ENABLED 0 |
#define WDT_CONFIG_LOG_LEVEL 3 |
#define WDT_CONFIG_RELOAD_VALUE 2000 |
#define WDT_ENABLED 0 |