PID_Reg Project Status
Project File: PID_Reg.ise Current State: Programming File Generated
Module Name: PID_Regulator
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
720 Warnings
Product Version: ISE 10.1.03 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
PID_Reg Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,921 9,312 20%  
Number of 4 input LUTs 8,491 9,312 91%  
Logic Distribution     
Number of occupied Slices 4,630 4,656 99%  
    Number of Slices containing only related logic 4,630 4,630 100%  
    Number of Slices containing unrelated logic 0 4,630 0%  
Total Number of 4 input LUTs 8,852 9,312 95%  
    Number used as logic 8,487      
    Number used as a route-thru 361      
    Number used as Shift registers 4      
Number of bonded IOBs
Number of bonded 39 232 16%  
Number of RAMB16s 20 20 100%  
Number of BUFGMUXs 3 24 12%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentfr 8. mai 07:43:18 20090237 Warnings14 Infos
Translation ReportCurrentfr 8. mai 07:43:50 2009015 Warnings0
Map ReportCurrentfr 8. mai 07:44:20 20090461 Warnings7 Infos
Place and Route ReportCurrentfr 8. mai 07:50:16 200907 Warnings3 Infos
Static Timing ReportCurrentfr 8. mai 07:50:36 2009003 Infos
Bitgen ReportCurrentfr 8. mai 07:51:02 20090457 Warnings0

Date Generated: 06/08/2009 - 21:05:41