PID_Reg Project Status (06/07/2009 - 20:08:09)
Project File: PID_Reg.ise Current State: Programming File Generated
Module Name: PID_Regulator
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
114 Warnings
Product Version: ISE 10.1.03 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
PID_Reg Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 374 9,312 4%  
Number of 4 input LUTs 942 9,312 10%  
Logic Distribution     
Number of occupied Slices 633 4,656 13%  
    Number of Slices containing only related logic 633 633 100%  
    Number of Slices containing unrelated logic 0 633 0%  
Total Number of 4 input LUTs 1,097 9,312 11%  
    Number used as logic 938      
    Number used as a route-thru 155      
    Number used as Shift registers 4      
Number of bonded IOBs
Number of bonded 39 232 16%  
Number of BUFGMUXs 3 24 12%  
Number of MULT18X18SIOs 8 20 40%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentsų 7. jun 20:06:37 2009094 Warnings10 Infos
Translation ReportCurrentsų 7. jun 20:06:54 200906 Warnings0
Map ReportCurrentsų 7. jun 20:07:04 200907 Warnings7 Infos
Place and Route ReportCurrentsų 7. jun 20:07:52 200907 Warnings5 Infos
Static Timing ReportCurrentsų 7. jun 20:07:58 2009003 Infos
Bitgen ReportCurrentsų 7. jun 20:08:09 200905 Warnings0

Date Generated: 06/07/2009 - 20:08:09