Design Overview for adder

PropertyValue
Project Name:d:\documents\ntnu\crayxd1\!fpwm\src\fpwm\par\xc2vp50
Target Device:xc2vp50
Report Generated:Tuesday 07/04/06 at 18:59
Printable Summary (View as HTML)adder_summary.html

Device Utilization Summary (estimated values)

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slices:140236160% 
Number of Slice Flip Flops:251472320% 
Number of 4 input LUTs:116472320% 
Number of bonded IOBs:15269221% 

Performance Summary

PropertyValue
Data Not Yet Available  

Failing Constraints

Constraint(s)RequestedActualLogic Levels
Data Not Yet Available   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentTuesday 07/04/06 at 18:59