Design Overview for top

PropertyValue
Project Name:d:\documents\ntnu\crayxd1\!fpwm\src\fpwm\par\xc2vp50
Target Device:xc2vp50
Constraints File:top.ucf
Report Generated:Tuesday 07/04/06 at 18:52
Printable Summary (View as HTML)top_summary.html

Device Utilization Summary (estimated values)

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slices:734236163% 
Number of Slice Flip Flops:1102472322% 
Number of 4 input LUTs:1082472322% 
Number of bonded IOBs:53469277% 
Number of GCLKs:21612% 
Number of DCM_ADVs:2825% 

Performance Summary

PropertyValue
Data Not Yet Available  

Failing Constraints

Constraint(s)RequestedActualLogic Levels
Data Not Yet Available   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentTuesday 07/04/06 at 18:52
Translation ReportOut-of-DateFriday 06/30/06 at 17:46
Map ReportOut-of-DateFriday 06/30/06 at 17:54
Pad ReportOut-of-DateFriday 06/30/06 at 18:10
Place and Route ReportOut-of-DateFriday 06/30/06 at 18:10
Post Place and Route Static Timing ReportOut-of-DateFriday 06/30/06 at 18:11
Bitgen ReportOut-of-DateFriday 06/30/06 at 18:15