EXTERNAL PORTS

These are the external ports defined in the MHS file.

Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB sys_clk_pin I 1 sys_clk_s  CLK  1GLB sys_rst_pin I 1 sys_rst_s  RESET  2A fpga_0_LEDS_GPIO_d_out_pin O 0:15 fpga_0_LEDS_GPIO_d_out 3B opb_offchip_memory_0_OMA_DATA_I_pin I 0:31 opb_offchip_memory_0_OMA_DATA_I 4B opb_offchip_memory_0_OMA_VALID_pin I 1 opb_offchip_memory_0_OMA_VALID 5B opb_offchip_memory_0_LEDS_DEBUG_pin O 0:15 opb_offchip_memory_0_LEDS_DEBUG 6B opb_offchip_memory_0_OMA_ACTIVE_pin O 1 opb_offchip_memory_0_OMA_ACTIVE 7B opb_offchip_memory_0_OMA_ADDRESS_pin O 0:31 opb_offchip_memory_0_OMA_ADDRESS 8B opb_offchip_memory_0_OMA_DATA_O_pin O 0:31 opb_offchip_memory_0_OMA_DATA_O 9B opb_offchip_memory_0_OMA_RW_pin O 1 opb_offchip_memory_0_OMA_RW