Change log for AXI S6 DDRx (AXI S6 MIG)


Changes in v1.06.a, introduced in 14.2

Note: Unless specified, limitations and resolved issues affect all previous versions.

14.2 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Updated S6 MIG PHYs and GUI to MIG release version 3.92.

  • See MIG version 3.92 release notes and documentation for more information about changes to MIG, supported FPGA devices, supported memory components, and board design information.

Resolved issues:
Known Issues / Limitations:

14.2 - Changes in tool interface files (.mpd)


14.2 - Changes in tool interface files (.pao)


14.2 - Changes in Tcl script files associated with core (.tcl)


14.2 - Changes in IP Configuration GUI (.ui)


14.2 - Changes in documentation associated with core


  • See Revision History tables in Spartan-6 MIG User Guide (UG416) and MCB User Guide (UG388).

Changes in v1.05.a, introduced in 13.4

Note: Unless specified, limitations and resolved issues affect all previous versions.

13.4 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Updated S6 MIG PHYs and GUI to MIG release version 3.91.

  • See MIG version 3.91 release notes and documentation for more information about changes to MIG, supported FPGA devices, supported memory components, and board design information.

Resolved issues:
Known Issues / Limitations:

13.4 - Changes in tool interface files (.mpd)


13.4 - Changes in tool interface files (.pao)


13.4 - Changes in Tcl script files associated with core (.tcl)


13.4 - Changes in IP Configuration GUI (.ui)


13.4 - Changes in documentation associated with core


  • See Revision History tables in Spartan-6 MIG User Guide (UG416) and MCB User Guide (UG388).

Changes in v1.04.a, introduced in 13.3

Note: Unless specified, limitations and resolved issues affect all previous versions.

13.3 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Updated S6 MIG PHYs and GUI to MIG release version 3.9.

  • See MIG version 3.9 release notes and documentation for more information about changes to MIG, supported FPGA devices, supported memory components, and board design information.

Resolved issues:
Known Issues / Limitations:

13.3 - Changes in tool interface files (.mpd)


13.3 - Changes in tool interface files (.pao)


  • Common AXI files renamed to avoid name space collisions with axi_interconnect in non-EDK environments.

13.3 - Changes in Tcl script files associated with core (.tcl)


  • [<CR618769>] UCF parsing updated to fix the warning message:

    The constraint is now converted properly.

13.3 - Changes in IP Configuration GUI (.ui)


13.3 - Changes in documentation associated with core


  • See Revision History tables in Spartan-6 MIG User Guide (UG416) and MCB User Guide (UG388).

Changes in v1.03.a, introduced in 13.2

Note: Unless specified, limitations and resolved issues affect all previous versions.

13.2 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Updated S6 MIG PHYs and GUI to MIG release version 3.8.

  • See MIG version 3.8 release notes and documentation for more information about changes to MIG, supported FPGA devices, supported memory components, and board design information.

Resolved issues:
  • [<CR602184>] Default value of parameter C_SIMULATION changed to TRUE. Parameter value is overwritten during platgen to a value of FALSE. This ensures that the optimal value of TRUE is used for simulation and that the required value of FALSE is set for synthesis.

Known Issues / Limitations:

13.2 - Changes in tool interface files (.mpd)


13.2 - Changes in tool interface files (.pao)


13.2 - Changes in Tcl script files associated with core (.tcl)


13.2 - Changes in IP Configuration GUI (.ui)


13.2 - Changes in documentation associated with core


  • See Revision History tables in Spartan-6 MIG User Guide (UG416) and MCB User Guide (UG388).

Changes in v1.02.a, introduced in 13.1

Note: Unless specified, limitations and resolved issues affect all previous versions.

13.1 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Updated S6/V6 MIG PHYs and GUI to MIG release version 3.7.

  • See MIG version 3.7 release notes and documentation for more information about changes to MIG, supported FPGA devices, supported memory components, and board design information.

Resolved issues:
  • [<CR585689>] Removed potential combinatorial paths between inputs and outputs of the same AXI Interface. Also ensure core can respond properly to an AXI transaction issued immediately after reset deassertion.

Known Issues / Limitations:

13.1 - Changes in tool interface files (.mpd)


13.1 - Changes in tool interface files (.pao)


13.1 - Changes in Tcl script files associated with core (.tcl)


13.1 - Changes in IP Configuration GUI (.ui)


13.1 - Changes in documentation associated with core


  • See Revision History tables in Spartan-6 MIG User Guide (UG416) and MCB User Guide (UG388).

Changes in v1.01.a, introduced in 12.4

Note: Unless specified, limitations and resolved issues affect all previous versions.

12.4 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Register Slices are automatically enabled based on device speed grade and AXI interface clock frequency to improve timing closure.

  • AXI Read/Write arbitration algorithm modified to improve throughput during simultaneous read and write AXI bursts of length greater than 16 beats.

  • Incremental size reduction and latency/timing improvement.

Resolved issues:
Known Issues / Limitations:

12.4 - Changes in tool interface files (.mpd)


  • Core state updated from Pre-Production to Production status.

12.4 - Changes in tool interface files (.pao)


12.4 - Changes in Tcl script files associated with core (.tcl)


  • TCL functions calculate register slices settings automatically based on device speed grade and AXI interface clock frequency.

12.4 - Changes in IP Configuration GUI (.ui)


12.4 - Changes in documentation associated with core




Changes in v1.00.a, introduced in 12.3

Note: Unless specified, limitations and resolved issues affect all previous versions.

12.3 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Initial Core Release.

Resolved issues:
Known Issues / Limitations:

12.3 - Changes in tool interface files (.mpd)


12.3 - Changes in tool interface files (.pao)


12.3 - Changes in Tcl script files associated with core (.tcl)


12.3 - Changes in IP Configuration GUI (.ui)


12.3 - Changes in documentation associated with core


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