Instruction Type:
Type_F3B
Decoder: op=2; op3=56; is=1;
ASM: [[[[['jmpl %reg + %imm, %reg', 'rs1', 'simm13', 'rd'], ['jmpl %imm + %reg, %reg', 'simm13', 'rs1', 'rd']], ['jmp %reg + %imm', 'rs1', 'simm13', 'rd', '%g0']], ['call %reg + %imm', 'rs1', 'simm13', 'rd', '%o7']], ['ret', 'rs1', '%i7', 'simm13', '8', 'rd', '%g0']]
ASM: ['retl', 'rs1', '%o7', 'simm13', '8', 'rd', '%g0']
Is Jump: readReg(rs1) + simm13
Delay: 1
Behavior: writeReg(rd, ac_pc);