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mips1 Architechture Description
mips1 Other Properties
ISA (ac_isa):
Name: mips1_isa.ac
Type_R (ac_format):
Format Description: op 6; rs 5; rt 5; rd 5; shamt 5; func 6;
Instructions: subu mflo mfhi instr_or instr_xor sll addu instr_break sys_call add mult jr srav sra divu nop instr_and sub instr_nor slt sllv srl sltu mthi mtlo srlv jalr div multu
Type_I (ac_format):
Format Description: op 6; rs 5; rt 5; imm 16 s;
Instructions: bltz bgezal lbu sw blez andi swl lwr bne lh lw lwl lui swr addi sltiu bgez ori xori lb bgtz addiu slti bltzal lhu sh sb beq
Type_J (ac_format):
Format Description: op 6; addr 26;
Instructions: j jal
bltz (ac_instr):
Instruction Type: Type_I
Decoder: op=1; rt=0;
ASM: bltz %reg, %exp(pcrel)
ASM: rs
ASM: imm
Is Branch: (ac_pc+4) + (imm<<2)
Delay: 1
Condition: RB[rs] & 0x80000000
bgezal (ac_instr):
Instruction Type: Type_I
Decoder: op=1; rt=17;
ASM: bgezal %reg, %exp(pcrel)
ASM: rs
ASM: imm
Is Branch: (ac_pc+4) + (imm<<2)
Delay: 1
Condition: !(RB[rs] & 0x80000000)
subu (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=35;
ASM: subu %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
lbu (ac_instr):
Instruction Type: Type_I
Decoder: op=36;
ASM: [['lbu %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['lbu %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['lbu %reg, %imm (%reg)', 'rt', 'imm', 'rs']
mflo (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=18;
ASM: mflo %reg
ASM: rd
sw (ac_instr):
Instruction Type: Type_I
Decoder: op=43;
ASM: [['sw %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['sw %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['sw %reg, %imm (%reg)', 'rt', 'imm', 'rs']
j (ac_instr):
Instruction Type: Type_J
Decoder: op=2;
ASM: j %exp(align)
ASM: addr
Is Jump: ((ac_pc+4) & 0xF0000000) | (addr<<2)
Delay: 1
mfhi (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=16;
ASM: mfhi %reg
ASM: rd
blez (ac_instr):
Instruction Type: Type_I
Decoder: op=6; rt=0;
ASM: blez %reg, %exp(pcrel)
ASM: rs
ASM: imm
Is Branch: (ac_pc+4) + (imm<<2)
Delay: 1
Condition: (RB[rs] == 0 ) || (RB[rs]&0x80000000 )
instr_or (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=37;
ASM: or %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
instr_xor (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=38;
ASM: xor %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
sll (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=0;
ASM: sll %reg, %reg, %imm
ASM: rd
ASM: rt
ASM: shamt
addu (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=33;
ASM: ['addu %reg, %reg, %reg', 'rd', 'rs', 'rt']
ASM: ['move %reg, %reg', 'rd', 'rs', 'rt', '$zero']
andi (ac_instr):
Instruction Type: Type_I
Decoder: op=12;
ASM: ['andi %reg, %reg, %imm', 'rt', 'rs', 'imm']
ASM: ['and %reg, %reg, %imm', 'rt', 'rs', 'imm']
swl (ac_instr):
Instruction Type: Type_I
Decoder: op=42;
ASM: ['swl %reg, (%reg)', 'rt', 'rs', 'imm', '0']
ASM: ['swl %reg, %imm (%reg)', 'rt', 'imm', 'rs']
instr_break (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=13;
ASM: ['break', 'rt', '0']
ASM: ['break %imm', 'rt']
lwr (ac_instr):
Instruction Type: Type_I
Decoder: op=38;
ASM: [['lwr %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['lwr %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['lwr %reg, %imm (%reg)', 'rt', 'imm', 'rs']
bne (ac_instr):
Instruction Type: Type_I
Decoder: op=5;
ASM: [['bgtu %reg, $0, %exp(pcrel)', 'rs', 'imm', 'rt', 0], ['bne %reg, %reg, %exp(pcrel)', 'rs', 'rt', 'imm']]
ASM: ['bnez %reg, %exp(pcrel)', 'rs', 'imm', 'rt', '0']
Is Branch: (ac_pc+4) + (imm<<2)
Delay: 1
Condition: RB[rs] != RB[rt]
sys_call (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=12;
ASM: syscall
jal (ac_instr):
Instruction Type: Type_J
Decoder: op=3;
ASM: jal %exp(align)
ASM: addr
Is Jump: ((ac_pc+4) & 0xF0000000) | (addr<<2)
Delay: 1
Behavior: RB[31] = (ac_pc+4)+4;
lh (ac_instr):
Instruction Type: Type_I
Decoder: op=33;
ASM: [['lh %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['lh %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['lh %reg, %imm (%reg)', 'rt', 'imm', 'rs']
lw (ac_instr):
Instruction Type: Type_I
Decoder: op=35;
ASM: [['lw %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['lw %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['lw %reg, %imm (%reg)', 'rt', 'imm', 'rs']
add (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=32;
ASM: add %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
mult (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=24;
ASM: mult %reg, %reg
ASM: rs
ASM: rt
lwl (ac_instr):
Instruction Type: Type_I
Decoder: op=34;
ASM: [['lwl %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['lwl %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['lwl %reg, %imm (%reg)', 'rt', 'imm', 'rs']
lui (ac_instr):
Instruction Type: Type_I
Decoder: op=15; rs=0;
ASM: [['lui %reg, %exp', 'rt', 'imm'], ['lui %reg, \\%hi(%imm(carry))', 'rt', 'imm']]
ASM: ['lui %reg, \\%hi(%exp(carry))', 'rt', 'imm']
swr (ac_instr):
Instruction Type: Type_I
Decoder: op=46;
ASM: ['swr %reg, (%reg)', 'rt', 'rs', 'imm', '0']
ASM: ['swr %reg, %imm (%reg)', 'rt', 'imm', 'rs']
addi (ac_instr):
Instruction Type: Type_I
Decoder: op=8;
ASM: ['addi %reg, %reg, %exp', 'rt', 'rs', 'imm']
ASM: ['add %reg, %reg, %exp', 'rt', 'rs', 'imm']
sltiu (ac_instr):
Instruction Type: Type_I
Decoder: op=11;
ASM: ['sltiu %reg, %reg, %exp', 'rt', 'rs', 'imm']
ASM: ['sltu %reg, %reg, %exp', 'rt', 'rs', 'imm']
bgez (ac_instr):
Instruction Type: Type_I
Decoder: op=1; rt=1;
ASM: bgez %reg, %exp(pcrel)
ASM: rs
ASM: imm
Is Branch: (ac_pc+4) + (imm<<2)
Delay: 1
Condition: !(RB[rs] & 0x80000000)
jr (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=8;
ASM: [['jr %reg', 'rs'], ['j %reg', 'rs']]
ASM: ['ret', 'rs', '$ra']
Is Jump: RB[rs]
Delay: 1
srav (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=7;
ASM: ['srav %reg, %reg, %reg', 'rd', 'rt', 'rs']
ASM: ['sra %reg, %reg, %reg', 'rd', 'rt', 'rs']
sra (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=3;
ASM: sra %reg, %reg, %imm
ASM: rd
ASM: rt
ASM: shamt
ori (ac_instr):
Instruction Type: Type_I
Decoder: op=13;
ASM: ['ori %reg, %reg, %imm', 'rt', 'rs', 'imm']
ASM: ['or %reg, %reg, %imm', 'rt', 'rs', 'imm']
xori (ac_instr):
Instruction Type: Type_I
Decoder: op=14;
ASM: ['xori %reg, %reg, %imm', 'rt', 'rs', 'imm']
ASM: ['xor %reg, %reg, %imm', 'rt', 'rs', 'imm']
lb (ac_instr):
Instruction Type: Type_I
Decoder: op=32;
ASM: [['lb %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['lb %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['lb %reg, %imm (%reg)', 'rt', 'imm', 'rs']
divu (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=27;
ASM: divu %reg, %reg
ASM: rs
ASM: rt
bgtz (ac_instr):
Instruction Type: Type_I
Decoder: op=7; rt=0;
ASM: bgtz %reg, %exp(pcrel)
ASM: rs
ASM: imm
Is Branch: (ac_pc+4) + (imm<<2)
Delay: 1
Condition: !(RB[rs] & 0x80000000) && (RB[rs]!=0)
nop (ac_instr):
Instruction Type: Type_R
Decoder: op=0; rd=0; func=0;
ASM: nop
ASM: rs
ASM: 0
ASM: rt
ASM: 0
ASM: shamt
ASM: 0
instr_and (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=36;
ASM: and %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
addiu (ac_instr):
Instruction Type: Type_I
Decoder: op=9;
ASM: [['addiu %reg, %reg, %exp', 'rt', 'rs', 'imm'], ['addiu %reg, %reg, \\%lo(%exp)', 'rt', 'rs', 'imm']]
ASM: ['addu %reg, %reg, %exp', 'rt', 'rs', 'imm']
sub (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=34;
ASM: sub %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
instr_nor (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=39;
ASM: nor %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
slt (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=42;
ASM: slt %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
sllv (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=4;
ASM: ['sllv %reg, %reg, %reg', 'rd', 'rt', 'rs']
ASM: ['sll %reg, %reg, %reg', 'rd', 'rt', 'rs']
slti (ac_instr):
Instruction Type: Type_I
Decoder: op=10;
ASM: ['slti %reg, %reg, %exp', 'rt', 'rs', 'imm']
ASM: ['slt %reg, %reg, %exp', 'rt', 'rs', 'imm']
bltzal (ac_instr):
Instruction Type: Type_I
Decoder: op=1; rt=16;
ASM: bltzal %reg, %exp(pcrel)
ASM: rs
ASM: imm
Is Branch: (ac_pc+4) + (imm<<2)
Delay: 1
Condition: RB[rs] & 0x80000000
srl (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=2;
ASM: srl %reg, %reg, %imm
ASM: rd
ASM: rt
ASM: shamt
sltu (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=43;
ASM: sltu %reg, %reg, %reg
ASM: rd
ASM: rs
ASM: rt
mthi (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=17;
ASM: mthi %reg
ASM: rs
lhu (ac_instr):
Instruction Type: Type_I
Decoder: op=37;
ASM: [['lhu %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['lhu %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['lhu %reg, %imm (%reg)', 'rt', 'imm', 'rs']
sh (ac_instr):
Instruction Type: Type_I
Decoder: op=41;
ASM: [['sh %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['sh %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['sh %reg, %imm (%reg)', 'rt', 'imm', 'rs']
mtlo (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=19;
ASM: mtlo %reg
ASM: rs
srlv (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=6;
ASM: ['srlv %reg, %reg, %reg', 'rd', 'rt', 'rs']
ASM: ['srl %reg, %reg, %reg', 'rd', 'rt', 'rs']
jalr (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=9;
ASM: [['jalr %reg, %reg', 'rd', 'rs'], ['jalr %reg', 'rs', 'rd', '$ra']]
ASM: ['jal %reg', 'rs', 'rd', '$ra']
Is Jump: RB[rs]
Delay: 1
Behavior: RB[(rd==0)?31:rd] = (ac_pc+4)+4;
sb (ac_instr):
Instruction Type: Type_I
Decoder: op=40;
ASM: [['sb %reg, \\%lo(%exp)(%reg)', 'rt', 'imm', 'rs'], ['sb %reg, (%reg)', 'rt', 'rs', 'imm', '0']]
ASM: ['sb %reg, %imm (%reg)', 'rt', 'imm', 'rs']
div (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=26;
ASM: div %reg, %reg
ASM: rs
ASM: rt
beq (ac_instr):
Instruction Type: Type_I
Decoder: op=4;
ASM: [['beq %reg, %reg, %exp(pcrel)', 'rs', 'rt', 'imm'], ['b %exp(pcrel)', 'imm', 'rs', '0', 'rt', '0']]
ASM: ['beqz %reg, %exp(pcrel)', 'rs', 'imm', 'rt', '0']
Is Branch: (ac_pc+4) + (imm<<2)
Delay: 1
Condition: RB[rs] == RB[rt]
multu (ac_instr):
Instruction Type: Type_R
Decoder: op=0; func=25;
ASM: multu %reg, %reg
ASM: rs
ASM: rt