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00028 #include "sparcv8_isa.H"
00029 #include "sparcv8_isa_init.cpp"
00030 #include "sparcv8_bhv_macros.H"
00031
00032
00033
00034 #include "ac_debug_model.H"
00035 #include "ansi-colors.h"
00036
00037
00038 using namespace sparcv8_parms;
00039
00041 void ac_behavior( instruction )
00042 {
00043 dbg_printf("----- PC=0x%x NPC=0x%x ----- #executed=%lld\n", (int) ac_pc, npc, ac_instr_counter);
00044 }
00045
00047 void ac_behavior( Type_F1 ){}
00048 void ac_behavior( Type_F2A ){}
00049 void ac_behavior( Type_F2B ){}
00050 void ac_behavior( Type_F3A ){}
00051 void ac_behavior( Type_F3B ){}
00052 void ac_behavior( Type_FT ){}
00053
00055
00056 #define writeReg(addr, val) REGS[addr] = (addr)? ac_word(val) : 0
00057 #define readReg(addr) (int)(REGS[addr])
00058
00059
00060 inline void update_pc(bool branch, bool taken, bool b_always, bool annul, ac_word addr, ac_reg<unsigned>& ac_pc, ac_reg<ac_word>& npc)
00061 {
00062
00063
00064
00065
00066 #ifdef AC_MEM_HIERARCHY
00067 if(!ac_wait_sig){
00068 #endif
00069 if (branch && (!taken ||b_always) && annul) {
00070 if (taken) {
00071 npc = addr;
00072 dbg_printf(CB_RED "Branch Taken" C_RESET LF);
00073 }
00074 else {
00075 npc+=4;
00076 }
00077 dbg_printf("Delay instruction annuled\n");
00078 ac_pc = npc;
00079 npc+=4;
00080 }
00081
00082 else {
00083 ac_pc = npc;
00084 if (taken) {
00085 npc = addr;
00086 dbg_printf(CB_RED "Branch Taken" C_RESET LF);
00087 }
00088 else {
00089 npc+=4;
00090 }
00091 }
00092 #ifdef AC_MEM_HIERARCHY
00093 }
00094 #endif
00095 }
00096
00097
00098
00099 #ifdef NO_NEED_PC_UPDATE
00100 #define update_pc(a,b,c,d,e, ac_pc, npc)
00101 #endif
00102
00103
00104 void trap_reg_window_overflow(ac_memory& DM, ac_regbank<256, ac_word, ac_Dword>& RB, ac_reg<unsigned char>& WIM)
00105 {
00106 WIM = (WIM-0x10);
00107 int sp = (WIM+14) & 0xFF;
00108 int l0 = (WIM+16) & 0xFF;
00109 for (int i=0; i<16; i++) {
00110 DM.write(RB.read(sp)+(i<<2), RB.read(l0+i));
00111 }
00112 }
00113
00114
00115 void trap_reg_window_underflow(ac_memory& DM, ac_regbank<256, ac_word, ac_Dword>& RB, ac_reg<unsigned char>& WIM)
00116 {
00117 int sp = (WIM+14) & 0xFF;
00118 int l0 = (WIM+16) & 0xFF;
00119 for (int i=0; i<16; i++) {
00120 RB.write(l0+i, DM.read(RB.read(sp)+(i<<2)));
00121 }
00122 WIM = (WIM+0x10);
00123 }
00124
00125
00127 void ac_behavior(begin)
00128 {
00129 dbg_printf("@@@ begin behavior @@@\n");
00130 REGS[0] = 0;
00131 npc = ac_pc + 4;
00132
00133 CWP = 0xF0;
00134 }
00135
00137 void ac_behavior(end)
00138 {
00139 dbg_printf("@@@ end behavior @@@\n");
00140 }
00141
00142
00143
00144
00145
00146
00148 void ac_behavior( call )
00149 {
00150 dbg_printf("call 0x%x\n", ac_pc+(disp30<<2));
00151 writeReg(15, ac_pc);
00152 update_pc(1,1,1,0, ac_pc+(disp30<<2), ac_pc, npc);
00153 };
00154
00156 void ac_behavior( nop )
00157 {
00158 dbg_printf("nop\n");
00159 update_pc(0,0,0,0,0, ac_pc, npc);
00160 };
00161
00163 void ac_behavior( sethi )
00164 {
00165 dbg_printf("sethi 0x%x,r%d\n", imm22, rd);
00166 writeReg(rd, (imm22 << 10));
00167 update_pc(0,0,0,0,0, ac_pc, npc);
00168 };
00169
00171 void ac_behavior( ba )
00172 {
00173 dbg_printf("ba 0x%x\n", ac_pc+(disp22<<2));
00174 update_pc(1,1,1,an, ac_pc+(disp22<<2), ac_pc, npc);
00175 };
00176
00178 void ac_behavior( bn )
00179 {
00180 dbg_printf("bn 0x%x\n", ac_pc+(disp22<<2));
00181 update_pc(1,0,0,an,0, ac_pc, npc);
00182 };
00183
00185 void ac_behavior( bne )
00186 {
00187 dbg_printf("bne 0x%x\n", ac_pc+(disp22<<2));
00188 update_pc(1, !PSR_icc_z, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00189 };
00190
00192 void ac_behavior( be )
00193 {
00194 dbg_printf("be 0x%x\n", ac_pc+(disp22<<2));
00195 update_pc(1, PSR_icc_z, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00196 };
00197
00199 void ac_behavior( bg )
00200 {
00201 dbg_printf("bg 0x%x\n", ac_pc+(disp22<<2));
00202 update_pc(1, !(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v)), 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00203 };
00204
00206 void ac_behavior( ble )
00207 {
00208 dbg_printf("ble 0x%x\n", ac_pc+(disp22<<2));
00209 update_pc(1, PSR_icc_z ||(PSR_icc_n ^PSR_icc_v), 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00210 };
00211
00213 void ac_behavior( bge )
00214 {
00215 dbg_printf("bge 0x%x\n", ac_pc+(disp22<<2));
00216 update_pc(1, !(PSR_icc_n ^PSR_icc_v), 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00217 };
00218
00220 void ac_behavior( bl )
00221 {
00222 dbg_printf("bl 0x%x\n", ac_pc+(disp22<<2));
00223 update_pc(1, PSR_icc_n ^PSR_icc_v, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00224 };
00225
00227 void ac_behavior( bgu )
00228 {
00229 dbg_printf("bgu 0x%x\n", ac_pc+(disp22<<2));
00230 update_pc(1, !(PSR_icc_c ||PSR_icc_z), 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00231 };
00232
00234 void ac_behavior( bleu )
00235 {
00236 dbg_printf("bleu 0x%x\n", ac_pc+(disp22<<2));
00237 update_pc(1, PSR_icc_c ||PSR_icc_z, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00238 };
00239
00241 void ac_behavior( bcc )
00242 {
00243 dbg_printf("bcc 0x%x\n", ac_pc+(disp22<<2));
00244 update_pc(1, !PSR_icc_c, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00245 };
00246
00248 void ac_behavior( bcs )
00249 {
00250 dbg_printf("bcs 0x%x\n", ac_pc+(disp22<<2));
00251 update_pc(1, PSR_icc_c, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00252 };
00253
00255 void ac_behavior( bpos )
00256 {
00257 dbg_printf("bpos 0x%x\n", ac_pc+(disp22<<2));
00258 update_pc(1, !PSR_icc_n, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00259 };
00260
00262 void ac_behavior( bneg )
00263 {
00264 dbg_printf("bneg 0x%x\n", ac_pc+(disp22<<2));
00265 update_pc(1, PSR_icc_n, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00266 };
00267
00269 void ac_behavior( bvc )
00270 {
00271 dbg_printf("bvc 0x%x\n", ac_pc+(disp22<<2));
00272 update_pc(1, !PSR_icc_v, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00273 };
00274
00276 void ac_behavior( bvs )
00277 {
00278 dbg_printf("bvs 0x%x\n", ac_pc+(disp22<<2));
00279 update_pc(1, PSR_icc_v, 0, an, ac_pc+(disp22<<2), ac_pc, npc);
00280 };
00281
00283 void ac_behavior( ldsb_reg )
00284 {
00285 dbg_printf("ldsb_reg [r%d+r%d], r%d\n", rs1, rs2, rd);
00286 writeReg(rd, (int)(char) DM.read_byte(readReg(rs1) + readReg(rs2)));
00287 dbg_printf("Result = 0x%x\n", readReg(rd));
00288 update_pc(0,0,0,0,0, ac_pc, npc);
00289 };
00290
00292 void ac_behavior( ldsh_reg )
00293 {
00294 dbg_printf("ldsh_reg [r%d+r%d], r%d\n", rs1, rs2, rd);
00295 writeReg(rd, (int)(short) DM.read_half(readReg(rs1) + readReg(rs2)));
00296 dbg_printf("Result = 0x%x\n", readReg(rd));
00297 update_pc(0,0,0,0,0, ac_pc, npc);
00298 };
00299
00301 void ac_behavior( ldub_reg )
00302 {
00303 dbg_printf("ldub_reg [r%d+r%d], r%d\n", rs1, rs2, rd);
00304 writeReg(rd, DM.read_byte(readReg(rs1) + readReg(rs2)));
00305 dbg_printf("Result = 0x%x\n", readReg(rd));
00306 update_pc(0,0,0,0,0, ac_pc, npc);
00307 };
00308
00310 void ac_behavior( lduh_reg )
00311 {
00312 dbg_printf("lduh_reg [r%d+r%d], r%d\n", rs1, rs2, rd);
00313 writeReg(rd, DM.read_half(readReg(rs1) + readReg(rs2)));
00314 dbg_printf("Result = 0x%x\n", readReg(rd));
00315 update_pc(0,0,0,0,0, ac_pc, npc);
00316 };
00317
00319 void ac_behavior( ld_reg )
00320 {
00321 dbg_printf("ld_reg [r%d+r%d], r%d\n", rs1, rs2, rd);
00322 writeReg(rd, DM.read(readReg(rs1) + readReg(rs2)));
00323 dbg_printf("Result = 0x%x\n", readReg(rd));
00324 update_pc(0,0,0,0,0, ac_pc, npc);
00325 };
00326
00328 void ac_behavior( ldd_reg )
00329 {
00330 dbg_printf("ldd_reg [r%d+r%d], r%d\n", rs1, rs2, rd);
00331 int tmp = DM.read(readReg(rs1) + readReg(rs2) + 4);
00332 writeReg(rd, DM.read(readReg(rs1) + readReg(rs2) ));
00333 writeReg(rd+1, tmp);
00334 dbg_printf("Result = 0x%x\n", readReg(rd));
00335 dbg_printf("Result = 0x%x\n", readReg(rd+1));
00336 update_pc(0,0,0,0,0, ac_pc, npc);
00337 };
00338
00340 void ac_behavior( stb_reg )
00341 {
00342 dbg_printf("stb_reg r%d, [r%d+r%d]\n", rd, rs1, rs2);
00343 DM.write_byte(readReg(rs1) + readReg(rs2), (char) readReg(rd));
00344 dbg_printf("Result = 0x%x\n", (char) readReg(rd));
00345 update_pc(0,0,0,0,0, ac_pc, npc);
00346 };
00347
00349 void ac_behavior( sth_reg )
00350 {
00351 dbg_printf("sth_reg r%d, [r%d+r%d]\n", rd, rs1, rs2);
00352 DM.write_half(readReg(rs1) + readReg(rs2), (short) readReg(rd));
00353 dbg_printf("Result = 0x%x\n", (short) readReg(rd));
00354 update_pc(0,0,0,0,0, ac_pc, npc);
00355 };
00356
00358 void ac_behavior( st_reg )
00359 {
00360 dbg_printf("st_reg r%d, [r%d+r%d]\n", rd, rs1, rs2);
00361 DM.write(readReg(rs1) + readReg(rs2), readReg(rd));
00362 dbg_printf("Result = 0x%x\n", readReg(rd));
00363 update_pc(0,0,0,0,0, ac_pc, npc);
00364 };
00365
00367 void ac_behavior( std_reg )
00368 {
00369 dbg_printf("std_reg r%d, [r%d+r%d]\n", rd, rs1, rs2);
00370 DM.write(readReg(rs1) + readReg(rs2), readReg(rd ));
00371 DM.write(readReg(rs1) + readReg(rs2) + 4, readReg(rd+1));
00372 dbg_printf("Result = 0x%x\n", readReg(rd));
00373 dbg_printf("Result = 0x%x\n", readReg(rd+1));
00374 update_pc(0,0,0,0,0, ac_pc, npc);
00375 };
00376
00378 void ac_behavior( ldstub_reg )
00379 {
00380 dbg_printf("atomic ldstub_reg r%d, [r%d+r%d]\n", rd, rs1, rs2);
00381 writeReg(rd, DM.read_byte(readReg(rs1) + readReg(rs2)));
00382 DM.write_byte(readReg(rs1) + readReg(rs2), 0xFF);
00383 update_pc(0,0,0,0,0, ac_pc, npc);
00384 };
00385
00387 void ac_behavior( swap_reg )
00388 {
00389 dbg_printf("swap_reg r%d, [r%d+r%d]\n", rd, rs1, rs2);
00390 int swap_temp = DM.read(readReg(rs1) + readReg(rs2));
00391 DM.write(readReg(rs1) + readReg(rs2), readReg(rd));
00392 writeReg(rd, swap_temp);
00393 update_pc(0,0,0,0,0, ac_pc, npc);
00394 };
00395
00397 void ac_behavior( sll_reg )
00398 {
00399 dbg_printf("sll_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00400 writeReg(rd, readReg(rs1) << readReg(rs2));
00401 dbg_printf("Result = 0x%x\n", readReg(rd));
00402 update_pc(0,0,0,0,0, ac_pc, npc);
00403 };
00404
00406 void ac_behavior( srl_reg )
00407 {
00408 dbg_printf("srl_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00409 writeReg(rd, ((unsigned) readReg(rs1)) >> ((unsigned) readReg(rs2)));
00410 dbg_printf("Result = 0x%x\n", readReg(rd));
00411 update_pc(0,0,0,0,0, ac_pc, npc);
00412 };
00413
00415 void ac_behavior( sra_reg )
00416 {
00417 dbg_printf("sra_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00418 writeReg(rd, ((int) readReg(rs1)) >> ((int) readReg(rs2)));
00419 dbg_printf("Result = 0x%x\n", readReg(rd));
00420 update_pc(0,0,0,0,0, ac_pc, npc);
00421 };
00422
00424 void ac_behavior( add_reg )
00425 {
00426 dbg_printf("add_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00427 writeReg(rd, readReg(rs1) + readReg(rs2));
00428 dbg_printf("Result = 0x%x\n", readReg(rd));
00429 update_pc(0,0,0,0,0, ac_pc, npc);
00430 };
00431
00433 void ac_behavior( addcc_reg )
00434 {
00435 dbg_printf("addcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00436 int dest = readReg(rs1) + readReg(rs2);
00437
00438 PSR_icc_n = dest >> 31;
00439 PSR_icc_z = dest == 0;
00440 PSR_icc_v = (( readReg(rs1) & readReg(rs2) & ~dest & 0x80000000) |
00441 (~readReg(rs1) & ~readReg(rs2) & dest & 0x80000000) );
00442 PSR_icc_c = ((readReg(rs1) & readReg(rs2) & 0x80000000) |
00443 (~dest & (readReg(rs1) | readReg(rs2)) & 0x80000000) );
00444
00445 writeReg(rd, dest);
00446 dbg_printf("Result = 0x%x\n", dest);
00447 update_pc(0,0,0,0,0, ac_pc, npc);
00448 };
00449
00451 void ac_behavior( addx_reg )
00452 {
00453 dbg_printf("addx_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00454 writeReg(rd, readReg(rs1) + readReg(rs2) + PSR_icc_c);
00455 dbg_printf("Result = 0x%x\n", readReg(rd));
00456 update_pc(0,0,0,0,0, ac_pc, npc);
00457 };
00458
00460 void ac_behavior( addxcc_reg )
00461 {
00462 dbg_printf("addxcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00463 int dest = readReg(rs1) + readReg(rs2) + PSR_icc_c;
00464
00465 PSR_icc_n = dest >> 31;
00466 PSR_icc_z = dest == 0;
00467 PSR_icc_v = (( readReg(rs1) & readReg(rs2) & ~dest & 0x80000000) |
00468 (~readReg(rs1) & ~readReg(rs2) & dest & 0x80000000) );
00469 PSR_icc_c = ((readReg(rs1) & readReg(rs2) & 0x80000000) |
00470 (~dest & (readReg(rs1) | readReg(rs2)) & 0x80000000) );
00471
00472 writeReg(rd, dest);
00473 dbg_printf("Result = 0x%x\n", dest);
00474 update_pc(0,0,0,0,0, ac_pc, npc);
00475 };
00476
00478 void ac_behavior( sub_reg )
00479 {
00480 dbg_printf("sub_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00481 writeReg(rd, (readReg(rs1) - readReg(rs2)));
00482 dbg_printf("Result = 0x%x\n", readReg(rd));
00483 update_pc(0,0,0,0,0, ac_pc, npc);
00484 };
00485
00487 void ac_behavior( subcc_reg )
00488 {
00489 dbg_printf("subcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00490 int dest = readReg(rs1) - readReg(rs2);
00491
00492 PSR_icc_n = dest >> 31;
00493 PSR_icc_z = dest == 0;
00494 PSR_icc_v = (( readReg(rs1) & ~readReg(rs2) & ~dest & 0x80000000) |
00495 (~readReg(rs1) & readReg(rs2) & dest & 0x80000000) );
00496 PSR_icc_c = ((~readReg(rs1) & readReg(rs2) & 0x80000000) |
00497 (dest & (~readReg(rs1) | readReg(rs2)) & 0x80000000) );
00498
00499 writeReg(rd, dest);
00500 dbg_printf("Result = 0x%x\n", dest);
00501 update_pc(0,0,0,0,0, ac_pc, npc);
00502 };
00503
00505 void ac_behavior( subx_reg )
00506 {
00507 dbg_printf("subx_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00508 writeReg(rd, readReg(rs1) - readReg(rs2) - PSR_icc_c);
00509 dbg_printf("Result = 0x%x\n", readReg(rd));
00510 update_pc(0,0,0,0,0, ac_pc, npc);
00511 };
00512
00514 void ac_behavior( subxcc_reg )
00515 {
00516 dbg_printf("subxcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00517 int dest = readReg(rs1) - readReg(rs2) - PSR_icc_c;
00518
00519 PSR_icc_n = dest >> 31;
00520 PSR_icc_z = dest == 0;
00521 PSR_icc_v = (( readReg(rs1) & ~readReg(rs2) & ~dest & 0x80000000) |
00522 (~readReg(rs1) & readReg(rs2) & dest & 0x80000000) );
00523 PSR_icc_c = ((~readReg(rs1) & readReg(rs2) & 0x80000000) |
00524 (dest & (~readReg(rs1) | readReg(rs2)) & 0x80000000) );
00525
00526 writeReg(rd, dest);
00527 dbg_printf("Result = 0x%x\n", dest);
00528 update_pc(0,0,0,0,0, ac_pc, npc);
00529 };
00530
00532 void ac_behavior( and_reg )
00533 {
00534 dbg_printf("and_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00535 writeReg(rd, readReg(rs1) & readReg(rs2));
00536 dbg_printf("Result = 0x%x\n", readReg(rd));
00537 update_pc(0,0,0,0,0, ac_pc, npc);
00538 };
00539
00541 void ac_behavior( andcc_reg )
00542 {
00543 dbg_printf("andcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00544 int dest = readReg(rs1) & readReg(rs2);
00545
00546 PSR_icc_n = dest >> 31;
00547 PSR_icc_z = dest == 0;
00548 PSR_icc_v = 0;
00549 PSR_icc_c = 0;
00550
00551 writeReg(rd, dest);
00552 dbg_printf("Result = 0x%x\n", dest);
00553 update_pc(0,0,0,0,0, ac_pc, npc);
00554 };
00555
00557 void ac_behavior( andn_reg )
00558 {
00559 dbg_printf("andn_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00560 writeReg(rd, readReg(rs1) & ~readReg(rs2));
00561 dbg_printf("Result = 0x%x\n", readReg(rd));
00562 update_pc(0,0,0,0,0, ac_pc, npc);
00563 };
00564
00566 void ac_behavior( andncc_reg )
00567 {
00568 dbg_printf("andncc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00569 int dest = readReg(rs1) & ~readReg(rs2);
00570
00571 PSR_icc_n = dest >> 31;
00572 PSR_icc_z = dest == 0;
00573 PSR_icc_v = 0;
00574 PSR_icc_c = 0;
00575
00576 writeReg(rd, dest);
00577 dbg_printf("Result = 0x%x\n", dest);
00578 update_pc(0,0,0,0,0, ac_pc, npc);
00579 };
00580
00582 void ac_behavior( or_reg )
00583 {
00584 dbg_printf("or_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00585 writeReg(rd, readReg(rs1) | readReg(rs2));
00586 dbg_printf("Result = 0x%x\n", readReg(rd));
00587 update_pc(0,0,0,0,0, ac_pc, npc);
00588 };
00589
00591 void ac_behavior( orcc_reg )
00592 {
00593 dbg_printf("orcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00594 int dest = readReg(rs1) | readReg(rs2);
00595
00596 PSR_icc_n = dest >> 31;
00597 PSR_icc_z = dest == 0;
00598 PSR_icc_v = 0;
00599 PSR_icc_c = 0;
00600
00601 writeReg(rd, dest);
00602 dbg_printf("Result = 0x%x\n", dest);
00603 update_pc(0,0,0,0,0, ac_pc, npc);
00604 };
00605
00607 void ac_behavior( orn_reg )
00608 {
00609 dbg_printf("orn_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00610 writeReg(rd, readReg(rs1) | ~readReg(rs2));
00611 dbg_printf("Result = 0x%x\n", readReg(rd));
00612 update_pc(0,0,0,0,0, ac_pc, npc);
00613 };
00614
00616 void ac_behavior( orncc_reg )
00617 {
00618 dbg_printf("orncc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00619 int dest = readReg(rs1) | ~readReg(rs2);
00620
00621 PSR_icc_n = dest >> 31;
00622 PSR_icc_z = dest == 0;
00623 PSR_icc_v = 0;
00624 PSR_icc_c = 0;
00625
00626 writeReg(rd, dest);
00627 dbg_printf("Result = 0x%x\n", dest);
00628 update_pc(0,0,0,0,0, ac_pc, npc);
00629 };
00630
00632 void ac_behavior( xor_reg )
00633 {
00634 dbg_printf("xor_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00635 writeReg(rd, readReg(rs1) ^ readReg(rs2));
00636 dbg_printf("Result = 0x%x\n", readReg(rd));
00637 update_pc(0,0,0,0,0, ac_pc, npc);
00638 };
00639
00641 void ac_behavior( xorcc_reg )
00642 {
00643 dbg_printf("xorcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00644 int dest = readReg(rs1) ^ readReg(rs2);
00645
00646 PSR_icc_n = dest >> 31;
00647 PSR_icc_z = dest == 0;
00648 PSR_icc_v = 0;
00649 PSR_icc_c = 0;
00650
00651 writeReg(rd, dest);
00652 dbg_printf("Result = 0x%x\n", dest);
00653 update_pc(0,0,0,0,0, ac_pc, npc);
00654 };
00655
00657 void ac_behavior( xnor_reg )
00658 {
00659 dbg_printf("xnor_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00660 writeReg(rd, ~(readReg(rs1) ^ readReg(rs2)));
00661 dbg_printf("Result = 0x%x\n", readReg(rd));
00662 update_pc(0,0,0,0,0, ac_pc, npc);
00663 };
00664
00666 void ac_behavior( xnorcc_reg )
00667 {
00668 dbg_printf("xnorcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00669 int dest = ~(readReg(rs1) ^ readReg(rs2));
00670
00671 PSR_icc_n = dest >> 31;
00672 PSR_icc_z = dest == 0;
00673 PSR_icc_v = 0;
00674 PSR_icc_c = 0;
00675
00676 writeReg(rd, dest);
00677 dbg_printf("Result = 0x%x\n", dest);
00678 update_pc(0,0,0,0,0, ac_pc, npc);
00679 };
00680
00682 void ac_behavior( save_reg )
00683 {
00684 dbg_printf("save_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00685 int tmp = readReg(rs1) + readReg(rs2);
00686
00687
00688 for (int i=16; i<32; i++) {
00689 RB.write((CWP + i) & 0xFF, REGS[i]);
00690 }
00691
00692
00693 for (int i=0; i<8; i++) {
00694 REGS[i+24] = REGS[i+8];
00695 }
00696
00697
00698 CWP = (CWP-0x10);
00699 if (CWP == WIM) trap_reg_window_overflow(DM, RB, WIM);
00700
00701
00702 for (int i=8; i<24; i++) {
00703 REGS[i] = RB.read((CWP + i) & 0xFF);
00704 }
00705
00706 writeReg(rd, tmp);
00707 dbg_printf(C_INVERSE "CWP: %d" C_RESET LF, CWP>>4);
00708 dbg_printf("Result = 0x%x\n", readReg(rd));
00709 update_pc(0,0,0,0,0, ac_pc, npc);
00710 };
00711
00713 void ac_behavior( restore_reg )
00714 {
00715 dbg_printf("restore_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00716 int tmp = readReg(rs1) + readReg(rs2);
00717
00718
00719 for (int i=8; i<24; i++) {
00720 RB.write((CWP + i) & 0xFF, REGS[i]);
00721 }
00722
00723
00724 for (int i=0; i<8; i++) {
00725 REGS[i+8] = REGS[i+24];
00726 }
00727
00728
00729 CWP = (CWP+0x10);
00730 if (CWP == WIM) trap_reg_window_underflow(DM, RB, WIM);
00731
00732
00733 for (int i=16; i<32; i++) {
00734 REGS[i] = RB.read((CWP + i) & 0xFF);
00735 }
00736
00737 writeReg(rd, tmp);
00738 dbg_printf(C_INVERSE "CWP: %d" C_RESET LF, CWP>>4);
00739 dbg_printf("Result = 0x%x\n", readReg(rd));
00740 update_pc(0,0,0,0,0, ac_pc, npc);
00741 };
00742
00744 void ac_behavior( umul_reg )
00745 {
00746 dbg_printf("umul_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00747 unsigned long long tmp = (unsigned long long) (unsigned) readReg(rs1) * (unsigned long long) (unsigned) readReg(rs2);
00748 writeReg(rd, (unsigned int) tmp);
00749 Y.write( (unsigned int) (tmp >> 32));
00750 dbg_printf("Result = 0x%x\n", readReg(rd));
00751 update_pc(0,0,0,0,0, ac_pc, npc);
00752 };
00753
00755 void ac_behavior( smul_reg )
00756 {
00757 dbg_printf("smul_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00758 long long tmp = (long long) readReg(rs1) * (long long) readReg(rs2);
00759 writeReg(rd, (int) tmp);
00760 Y.write( (int) (tmp >> 32));
00761 dbg_printf("Result = 0x%x\n", readReg(rd));
00762 update_pc(0,0,0,0,0, ac_pc, npc);
00763 };
00764
00766 void ac_behavior( umulcc_reg )
00767 {
00768 dbg_printf("umul_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00769 unsigned long long tmp = (unsigned long long) (unsigned) readReg(rs1) * (unsigned long long) (unsigned) readReg(rs2);
00770
00771 PSR_icc_n = (unsigned int) tmp >> 31;
00772 PSR_icc_z = (unsigned int) tmp == 0;
00773 PSR_icc_v = 0;
00774 PSR_icc_c = 0;
00775
00776 writeReg(rd, (unsigned int) tmp);
00777 Y.write( (unsigned int) (tmp >> 32));
00778 dbg_printf("Result = 0x%x\n", readReg(rd));
00779 update_pc(0,0,0,0,0, ac_pc, npc);
00780 };
00781
00783 void ac_behavior( smulcc_reg )
00784 {
00785 dbg_printf("smulcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00786 long long tmp = (long long) readReg(rs1) * (long long) readReg(rs2);
00787
00788 PSR_icc_n = (unsigned int) tmp >> 31;
00789 PSR_icc_z = (unsigned int) tmp == 0;
00790 PSR_icc_v = 0;
00791 PSR_icc_c = 0;
00792
00793 writeReg(rd, (int) tmp);
00794 Y.write( (int) (tmp >> 32));
00795 dbg_printf("Result = 0x%x\n", readReg(rd));
00796 update_pc(0,0,0,0,0, ac_pc, npc);
00797 };
00798
00800 void ac_behavior( udiv_reg )
00801 {
00802 dbg_printf("udiv_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00803 unsigned long long tmp;
00804 tmp = (unsigned long long) Y.read() << 32;
00805 tmp |= (unsigned) readReg(rs1);
00806 tmp /= (unsigned int) readReg(rs2);
00807 unsigned int result = tmp & 0xFFFFFFFF;
00808 bool temp_v = ((tmp >> 32) == 0) ? 0 : 1;
00809 if (temp_v) result = 0xFFFFFFFF;
00810 writeReg(rd, result);
00811 dbg_printf("Result = 0x%x\n", readReg(rd));
00812 update_pc(0,0,0,0,0, ac_pc, npc);
00813 };
00814
00816 void ac_behavior( udivcc_reg )
00817 {
00818 dbg_printf("udivcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00819 unsigned long long tmp;
00820 tmp = (unsigned long long) Y.read() << 32;
00821 tmp |= (unsigned) readReg(rs1);
00822 tmp /= (unsigned int) readReg(rs2);
00823 unsigned int result = tmp & 0xFFFFFFFF;
00824 bool temp_v = ((tmp >> 32) == 0) ? 0 : 1;
00825 if (temp_v) result = 0xFFFFFFFF;
00826
00827 PSR_icc_n = result >> 31;
00828 PSR_icc_z = result == 0;
00829 PSR_icc_v = temp_v;
00830 PSR_icc_c = 0;
00831
00832 writeReg(rd, result);
00833 dbg_printf("Result = 0x%x\n", readReg(rd));
00834 update_pc(0,0,0,0,0, ac_pc, npc);
00835 };
00836
00838 void ac_behavior( sdiv_reg )
00839 {
00840 dbg_printf("sdiv_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00841 long long tmp;
00842 tmp = (unsigned long long) Y.read() << 32;
00843 tmp |= (unsigned) readReg(rs1);
00844 tmp /= (signed) readReg(rs2);
00845 int result = tmp & 0xFFFFFFFF;
00846 bool temp_v = (((tmp >> 31) == 0) |
00847 ((tmp >> 31) == -1LL)) ? 0 : 1;
00848 if (temp_v) {
00849 if (tmp > 0) result = 0x7FFFFFFF;
00850 else result = 0x80000000;
00851 }
00852 writeReg(rd, result);
00853 dbg_printf("Result = 0x%x\n", readReg(rd));
00854 update_pc(0,0,0,0,0, ac_pc, npc);
00855 };
00856
00858 void ac_behavior( sdivcc_reg )
00859 {
00860 dbg_printf("sdivcc_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00861 long long tmp;
00862 tmp = (unsigned long long) Y.read() << 32;
00863 tmp |= (unsigned) readReg(rs1);
00864 tmp /= (signed) readReg(rs2);
00865 int result = tmp & 0xFFFFFFFF;
00866 bool temp_v = (((tmp >> 31) == 0) |
00867 ((tmp >> 31) == -1LL)) ? 0 : 1;
00868 if (temp_v) {
00869 if (tmp > 0) result = 0x7FFFFFFF;
00870 else result = 0x80000000;
00871 }
00872
00873 PSR_icc_n = result >> 31;
00874 PSR_icc_z = result == 0;
00875 PSR_icc_v = temp_v;
00876 PSR_icc_c = 0;
00877
00878 writeReg(rd, result);
00879 dbg_printf("Result = 0x%x\n", readReg(rd));
00880 update_pc(0,0,0,0,0, ac_pc, npc);
00881 };
00882
00884 void ac_behavior( jmpl_reg )
00885 {
00886 dbg_printf("jmpl_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00887 writeReg(rd, ac_pc);
00888
00889 update_pc(1,1,1,0, readReg(rs1) + readReg(rs2), ac_pc, npc);
00890 };
00891
00893 void ac_behavior( wry_reg )
00894 {
00895 dbg_printf("wry_reg r%d,r%d,r%d\n", rs1, rs2, rd);
00896 Y.write( readReg(rs1) ^ readReg(rs2));
00897 update_pc(0,0,0,0,0, ac_pc, npc);
00898 };
00899
00901 void ac_behavior( ldsb_imm )
00902 {
00903 dbg_printf("ldsb_imm [r%d + %d], r%d\n", rs1, simm13, rd);
00904 writeReg(rd, (int)(char) DM.read_byte(readReg(rs1) + simm13));
00905 dbg_printf("Result = 0x%x\n", readReg(rd));
00906 update_pc(0,0,0,0,0, ac_pc, npc);
00907 };
00908
00910 void ac_behavior( ldsh_imm )
00911 {
00912 dbg_printf("ldsh_imm [r%d + %d], r%d\n", rs1, simm13, rd);
00913 writeReg(rd, (int)(short) DM.read_half(readReg(rs1) + simm13));
00914 dbg_printf("Result = 0x%x\n", readReg(rd));
00915 update_pc(0,0,0,0,0, ac_pc, npc);
00916 };
00917
00919 void ac_behavior( ldub_imm )
00920 {
00921 dbg_printf("ldub_imm [r%d + %d], r%d\n", rs1, simm13, rd);
00922 writeReg(rd, DM.read_byte(readReg(rs1) + simm13));
00923 dbg_printf("Result = 0x%x\n", readReg(rd));
00924 update_pc(0,0,0,0,0, ac_pc, npc);
00925 };
00926
00928 void ac_behavior( lduh_imm )
00929 {
00930 dbg_printf("lduh_imm [r%d + %d], r%d\n", rs1, simm13, rd);
00931 writeReg(rd, DM.read_half(readReg(rs1) + simm13));
00932 dbg_printf("Result = 0x%x\n", readReg(rd));
00933 update_pc(0,0,0,0,0, ac_pc, npc);
00934 };
00935
00937 void ac_behavior( ld_imm )
00938 {
00939 dbg_printf("ld_imm [r%d + %d], r%d\n", rs1, simm13, rd);
00940 writeReg(rd, DM.read(readReg(rs1) + simm13));
00941 dbg_printf("Result = 0x%x\n", readReg(rd));
00942 update_pc(0,0,0,0,0, ac_pc, npc);
00943 };
00944
00946 void ac_behavior( ldd_imm )
00947 {
00948 dbg_printf("ldd_imm [r%d + %d], r%d\n", rs1, simm13, rd);
00949 int tmp = DM.read(readReg(rs1) + simm13 + 4);
00950 writeReg(rd, DM.read(readReg(rs1) + simm13));
00951 writeReg(rd+1, tmp);
00952 dbg_printf("Result = 0x%x\n", readReg(rd));
00953 dbg_printf("Result = 0x%x\n", readReg(rd+1));
00954 update_pc(0,0,0,0,0, ac_pc, npc);
00955 };
00956
00958 void ac_behavior( and_imm )
00959 {
00960 dbg_printf("and_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
00961 writeReg(rd, readReg(rs1) & simm13);
00962 dbg_printf("Result = 0x%x\n", readReg(rd));
00963 update_pc(0,0,0,0,0, ac_pc, npc);
00964 };
00965
00967 void ac_behavior( andcc_imm )
00968 {
00969 dbg_printf("andcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
00970 int dest = readReg(rs1) & simm13;
00971
00972 PSR_icc_n = dest >> 31;
00973 PSR_icc_z = dest == 0;
00974 PSR_icc_v = 0;
00975 PSR_icc_c = 0;
00976
00977 writeReg(rd, dest);
00978 dbg_printf("Result = 0x%x\n", dest);
00979 update_pc(0,0,0,0,0, ac_pc, npc);
00980 };
00981
00983 void ac_behavior( andn_imm )
00984 {
00985 dbg_printf("andn_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
00986 writeReg(rd, readReg(rs1) & ~simm13);
00987 dbg_printf("Result = 0x%x\n", readReg(rd));
00988 update_pc(0,0,0,0,0, ac_pc, npc);
00989 };
00990
00992 void ac_behavior( andncc_imm )
00993 {
00994 dbg_printf("andncc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
00995 int dest = readReg(rs1) & ~simm13;
00996
00997 PSR_icc_n = dest >> 31;
00998 PSR_icc_z = dest == 0;
00999 PSR_icc_v = 0;
01000 PSR_icc_c = 0;
01001
01002 writeReg(rd, dest);
01003 dbg_printf("Result = 0x%x\n", dest);
01004 update_pc(0,0,0,0,0, ac_pc, npc);
01005 };
01006
01008 void ac_behavior( or_imm )
01009 {
01010 dbg_printf("or_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01011 writeReg(rd, readReg(rs1) | simm13);
01012 dbg_printf("Result = 0x%x\n", readReg(rd));
01013 update_pc(0,0,0,0,0, ac_pc, npc);
01014 };
01015
01017 void ac_behavior( orcc_imm )
01018 {
01019 dbg_printf("orcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01020 int dest = readReg(rs1) | simm13;
01021
01022 PSR_icc_n = dest >> 31;
01023 PSR_icc_z = dest == 0;
01024 PSR_icc_v = 0;
01025 PSR_icc_c = 0;
01026
01027 writeReg(rd, dest);
01028 dbg_printf("Result = 0x%x\n", dest);
01029 update_pc(0,0,0,0,0, ac_pc, npc);
01030 };
01031
01033 void ac_behavior( orn_imm )
01034 {
01035 dbg_printf("orn_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01036 writeReg(rd, readReg(rs1) | ~simm13);
01037 dbg_printf("Result = 0x%x\n", readReg(rd));
01038 update_pc(0,0,0,0,0, ac_pc, npc);
01039 };
01040
01042 void ac_behavior( orncc_imm )
01043 {
01044 dbg_printf("orn_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01045 int dest = readReg(rs1) | ~simm13;
01046
01047 PSR_icc_n = dest >> 31;
01048 PSR_icc_z = dest == 0;
01049 PSR_icc_v = 0;
01050 PSR_icc_c = 0;
01051
01052 writeReg(rd, dest);
01053 dbg_printf("Result = 0x%x\n", dest);
01054 update_pc(0,0,0,0,0, ac_pc, npc);
01055 };
01056
01058 void ac_behavior( xor_imm )
01059 {
01060 dbg_printf("xor_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01061 writeReg(rd, readReg(rs1) ^ simm13);
01062 dbg_printf("Result = 0x%x\n", readReg(rd));
01063 update_pc(0,0,0,0,0, ac_pc, npc);
01064 };
01065
01067 void ac_behavior( xorcc_imm )
01068 {
01069 dbg_printf("xorcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01070 int dest = readReg(rs1) ^ simm13;
01071
01072 PSR_icc_n = dest >> 31;
01073 PSR_icc_z = dest == 0;
01074 PSR_icc_v = 0;
01075 PSR_icc_c = 0;
01076
01077 writeReg(rd, dest);
01078 dbg_printf("Result = 0x%x\n", dest);
01079 update_pc(0,0,0,0,0, ac_pc, npc);
01080 };
01081
01083 void ac_behavior( xnor_imm )
01084 {
01085 dbg_printf("xnor_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01086 writeReg(rd, ~(readReg(rs1) ^ simm13));
01087 dbg_printf("Result = 0x%x\n", readReg(rd));
01088 update_pc(0,0,0,0,0, ac_pc, npc);
01089 };
01090
01092 void ac_behavior( xnorcc_imm )
01093 {
01094 dbg_printf("xnorcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01095 int dest = ~(readReg(rs1) ^ simm13);
01096
01097 PSR_icc_n = dest >> 31;
01098 PSR_icc_z = dest == 0;
01099 PSR_icc_v = 0;
01100 PSR_icc_c = 0;
01101
01102 writeReg(rd, dest);
01103 dbg_printf("Result = 0x%x\n", dest);
01104 update_pc(0,0,0,0,0, ac_pc, npc);
01105 };
01106
01108 void ac_behavior( umul_imm )
01109 {
01110 dbg_printf("umul_imm r%d,%d,r%d\n", rs1, simm13, rd);
01111 unsigned long long tmp = (unsigned long long) (unsigned) readReg(rs1) * (unsigned long long) (unsigned) simm13;
01112 writeReg(rd, (unsigned int) tmp);
01113 Y.write( (unsigned int) (tmp >> 32));
01114 dbg_printf("Result = 0x%x\n", readReg(rd));
01115 update_pc(0,0,0,0,0, ac_pc, npc);
01116 };
01117
01119 void ac_behavior( smul_imm )
01120 {
01121 dbg_printf("smul_imm r%d,%d,r%d\n", rs1, simm13, rd);
01122 long long tmp = (long long) readReg(rs1) * (long long) simm13;
01123 writeReg(rd, (int) tmp);
01124 Y.write( (int) (tmp >> 32));
01125 dbg_printf("Result = 0x%x\n", readReg(rd));
01126 update_pc(0,0,0,0,0, ac_pc, npc);
01127 };
01128
01130 void ac_behavior( umulcc_imm )
01131 {
01132 dbg_printf("umulcc_imm r%d,%d,r%d\n", rs1, simm13, rd);
01133 unsigned long long tmp = (unsigned long long) (unsigned) readReg(rs1) * (unsigned long long) (unsigned) simm13;
01134
01135 PSR_icc_n = (unsigned int) tmp >> 31;
01136 PSR_icc_z = (unsigned int) tmp == 0;
01137 PSR_icc_v = 0;
01138 PSR_icc_c = 0;
01139
01140 writeReg(rd, (unsigned int) tmp);
01141 Y.write( (unsigned int) (tmp >> 32));
01142 dbg_printf("Result = 0x%x\n", readReg(rd));
01143 update_pc(0,0,0,0,0, ac_pc, npc);
01144 };
01145
01147 void ac_behavior( smulcc_imm )
01148 {
01149 dbg_printf("smulcc_imm r%d,%d,r%d\n", rs1, simm13, rd);
01150 long long tmp = (long long) readReg(rs1) * (long long) simm13;
01151
01152 PSR_icc_n = (unsigned int) tmp >> 31;
01153 PSR_icc_z = (unsigned int) tmp == 0;
01154 PSR_icc_v = 0;
01155 PSR_icc_c = 0;
01156
01157 writeReg(rd, (int) tmp);
01158 Y.write( (int) (tmp >> 32));
01159 dbg_printf("Result = 0x%x\n", readReg(rd));
01160 update_pc(0,0,0,0,0, ac_pc, npc);
01161 };
01162
01164 void ac_behavior( udiv_imm )
01165 {
01166 dbg_printf("udiv_imm r%d,%d,r%d\n", rs1, simm13, rd);
01167 unsigned long long tmp;
01168 tmp = (unsigned long long) Y.read() << 32;
01169 tmp |= (unsigned) readReg(rs1);
01170 tmp /= (unsigned int) simm13;
01171 unsigned int result = tmp & 0xFFFFFFFF;
01172 bool temp_v = ((tmp >> 32) == 0) ? 0 : 1;
01173 if (temp_v) result = 0xFFFFFFFF;
01174 writeReg(rd, result);
01175 dbg_printf("Result = 0x%x\n", readReg(rd));
01176 update_pc(0,0,0,0,0, ac_pc, npc);
01177 };
01178
01180 void ac_behavior( udivcc_imm )
01181 {
01182 dbg_printf("udivcc_imm r%d,%d,r%d\n", rs1, simm13, rd);
01183 unsigned long long tmp;
01184 tmp = (unsigned long long) Y.read() << 32;
01185 tmp |= (unsigned) readReg(rs1);
01186 tmp /= (unsigned int) simm13;
01187 unsigned int result = tmp & 0xFFFFFFFF;
01188 bool temp_v = ((tmp >> 32) == 0) ? 0 : 1;
01189 if (temp_v) result = 0xFFFFFFFF;
01190
01191 PSR_icc_n = result >> 31;
01192 PSR_icc_z = result == 0;
01193 PSR_icc_v = temp_v;
01194 PSR_icc_c = 0;
01195
01196 writeReg(rd, result);
01197 dbg_printf("Result = 0x%x\n", readReg(rd));
01198 update_pc(0,0,0,0,0, ac_pc, npc);
01199 };
01200
01202 void ac_behavior( sdiv_imm )
01203 {
01204 dbg_printf("sdiv_imm r%d,%d,r%d\n", rs1, simm13, rd);
01205 long long tmp;
01206 tmp = (unsigned long long) Y.read() << 32;
01207 tmp |= (unsigned) readReg(rs1);
01208 tmp /= (signed) simm13;
01209 int result = tmp & 0xFFFFFFFF;
01210 bool temp_v = (((tmp >> 31) == 0) |
01211 ((tmp >> 31) == -1LL)) ? 0 : 1;
01212 if (temp_v) {
01213 if (tmp > 0) result = 0x7FFFFFFF;
01214 else result = 0x80000000;
01215 }
01216 writeReg(rd, result);
01217 dbg_printf("Result = 0x%x\n", readReg(rd));
01218 update_pc(0,0,0,0,0, ac_pc, npc);
01219 };
01220
01222 void ac_behavior( sdivcc_imm )
01223 {
01224 dbg_printf("sdivcc_imm r%d,%d,r%d\n", rs1, simm13, rd);
01225 long long tmp;
01226 tmp = (unsigned long long) Y.read() << 32;
01227 tmp |= (unsigned) readReg(rs1);
01228 tmp /= simm13;
01229 int result = tmp & 0xFFFFFFFF;
01230 bool temp_v = (((tmp >> 31) == 0) |
01231 ((tmp >> 31) == -1LL)) ? 0 : 1;
01232 if (temp_v) {
01233 if (tmp > 0) result = 0x7FFFFFFF;
01234 else result = 0x80000000;
01235 }
01236
01237 PSR_icc_n = result >> 31;
01238 PSR_icc_z = result == 0;
01239 PSR_icc_v = temp_v;
01240 PSR_icc_c = 0;
01241
01242 writeReg(rd, result);
01243 dbg_printf("Result = 0x%x\n", readReg(rd));
01244 update_pc(0,0,0,0,0, ac_pc, npc);
01245 };
01246
01248 void ac_behavior( stb_imm )
01249 {
01250 dbg_printf("stb_imm r%d, [r%d + %d]\n", rd, rs1, simm13);
01251 DM.write_byte(readReg(rs1) + simm13, (char) readReg(rd));
01252 dbg_printf("Result = 0x%x\n", (char) readReg(rd));
01253 update_pc(0,0,0,0,0, ac_pc, npc);
01254 };
01255
01257 void ac_behavior( sth_imm )
01258 {
01259 dbg_printf("sth_imm r%d, [r%d + %d]\n", rd, rs1, simm13);
01260 DM.write_half(readReg(rs1) + simm13, (short) readReg(rd));
01261 dbg_printf("Result = 0x%x\n", (short) readReg(rd));
01262 update_pc(0,0,0,0,0, ac_pc, npc);
01263 };
01264
01266 void ac_behavior( st_imm )
01267 {
01268 dbg_printf("st_imm r%d, [r%d + %d]\n", rd, rs1, simm13);
01269 DM.write(readReg(rs1) + simm13, readReg(rd));
01270 dbg_printf("Result = 0x%x\n", readReg(rd));
01271 update_pc(0,0,0,0,0, ac_pc, npc);
01272 };
01273
01275 void ac_behavior( std_imm )
01276 {
01277 dbg_printf("std_imm r%d, [r%d + %d]\n", rd, rs1, simm13);
01278 DM.write(readReg(rs1) + simm13, readReg(rd ));
01279 DM.write(readReg(rs1) + simm13 + 4, readReg(rd+1));
01280 dbg_printf("Result = 0x%x\n", readReg(rd));
01281 dbg_printf("Result = 0x%x\n", readReg(rd+1));
01282 update_pc(0,0,0,0,0, ac_pc, npc);
01283 };
01284
01286 void ac_behavior( ldstub_imm )
01287 {
01288 dbg_printf("atomic ldstub_imm r%d, [r%d + %d]\n", rd, rs1, simm13);
01289 writeReg(rd, DM.read_byte(readReg(rs1) + simm13));
01290 DM.write_byte(readReg(rs1) + simm13, 0xFF);
01291 update_pc(0,0,0,0,0, ac_pc, npc);
01292 };
01293
01295 void ac_behavior( swap_imm )
01296 {
01297 dbg_printf("swap_imm r%d, [r%d + %d]\n", rd, rs1, simm13);
01298 int swap_temp = DM.read(readReg(rs1) + simm13);
01299 DM.write(readReg(rs1) + simm13, readReg(rd));
01300 writeReg(rd, swap_temp);
01301 update_pc(0,0,0,0,0, ac_pc, npc);
01302 };
01303
01305 void ac_behavior( sll_imm )
01306 {
01307 dbg_printf("sll_imm r%d,%d,r%d\n", rs1, simm13, rd);
01308 writeReg(rd, readReg(rs1) << simm13);
01309 dbg_printf("Result = 0x%x\n", readReg(rd));
01310 update_pc(0,0,0,0,0, ac_pc, npc);
01311 };
01312
01314 void ac_behavior( srl_imm )
01315 {
01316 dbg_printf("srl_imm r%d,%d,r%d\n", rs1, simm13, rd);
01317 writeReg(rd, ((unsigned) readReg(rs1)) >> ((unsigned) simm13));
01318 dbg_printf("Result = 0x%x\n", readReg(rd));
01319 update_pc(0,0,0,0,0, ac_pc, npc);
01320 };
01321
01323 void ac_behavior( sra_imm )
01324 {
01325 dbg_printf("sra_imm r%d,%d,r%d\n", rs1, simm13, rd);
01326 writeReg(rd, ((int) readReg(rs1)) >> simm13 );
01327 dbg_printf("Result = 0x%x\n", readReg(rd));
01328 update_pc(0,0,0,0,0, ac_pc, npc);
01329 };
01330
01332 void ac_behavior( add_imm )
01333 {
01334 dbg_printf("add_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01335 writeReg(rd, readReg(rs1) + simm13);
01336 dbg_printf("Result = 0x%x\n", readReg(rd));
01337 update_pc(0,0,0,0,0, ac_pc, npc);
01338 };
01339
01341 void ac_behavior( addcc_imm )
01342 {
01343 dbg_printf("addcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01344 int dest = readReg(rs1) + simm13;
01345
01346 PSR_icc_n = dest >> 31;
01347 PSR_icc_z = dest == 0;
01348 PSR_icc_v = (( readReg(rs1) & simm13 & ~dest & 0x80000000) |
01349 (~readReg(rs1) & ~simm13 & dest & 0x80000000) );
01350 PSR_icc_c = ((readReg(rs1) & simm13 & 0x80000000) |
01351 (~dest & (readReg(rs1) | simm13) & 0x80000000) );
01352
01353 writeReg(rd, dest);
01354 dbg_printf("Result = 0x%x\n", dest);
01355 update_pc(0,0,0,0,0, ac_pc, npc);
01356 };
01357
01359 void ac_behavior( addx_imm )
01360 {
01361 dbg_printf("addx_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01362 writeReg(rd, readReg(rs1) + simm13 + PSR_icc_c);
01363 dbg_printf("Result = 0x%x\n", readReg(rd));
01364 update_pc(0,0,0,0,0, ac_pc, npc);
01365 };
01366
01368 void ac_behavior( addxcc_imm )
01369 {
01370 dbg_printf("addxcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01371 int dest = readReg(rs1) + simm13 + PSR_icc_c;
01372
01373 PSR_icc_n = dest >> 31;
01374 PSR_icc_z = dest == 0;
01375 PSR_icc_v = (( readReg(rs1) & simm13 & ~dest & 0x80000000) |
01376 (~readReg(rs1) & ~simm13 & dest & 0x80000000) );
01377 PSR_icc_c = ((readReg(rs1) & simm13 & 0x80000000) |
01378 (~dest & (readReg(rs1) | simm13) & 0x80000000) );
01379
01380 writeReg(rd, dest);
01381 dbg_printf("Result = 0x%x\n", dest);
01382 update_pc(0,0,0,0,0, ac_pc, npc);
01383 };
01384
01386 void ac_behavior( sub_imm )
01387 {
01388 dbg_printf("sub_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01389 writeReg(rd, readReg(rs1) - simm13);
01390 dbg_printf("Result = 0x%x\n", readReg(rd));
01391 update_pc(0,0,0,0,0, ac_pc, npc);
01392 };
01393
01395 void ac_behavior( subcc_imm )
01396 {
01397 dbg_printf("subcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01398 int dest = readReg(rs1) - simm13;
01399
01400 PSR_icc_n = dest >> 31;
01401 PSR_icc_z = dest == 0;
01402 PSR_icc_v = (( readReg(rs1) & ~simm13 & ~dest & 0x80000000) |
01403 (~readReg(rs1) & simm13 & dest & 0x80000000) );
01404 PSR_icc_c = ((~readReg(rs1) & simm13 & 0x80000000) |
01405 (dest & (~readReg(rs1) | simm13) & 0x80000000) );
01406
01407 writeReg(rd, dest);
01408 dbg_printf("Result = 0x%x\n", dest);
01409 update_pc(0,0,0,0,0, ac_pc, npc);
01410 };
01411
01413 void ac_behavior( subx_imm )
01414 {
01415 dbg_printf("subx_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01416 writeReg(rd, readReg(rs1) - simm13 - PSR_icc_c);
01417 dbg_printf("Result = 0x%x\n", readReg(rd));
01418 update_pc(0,0,0,0,0, ac_pc, npc);
01419 };
01420
01422 void ac_behavior( subxcc_imm )
01423 {
01424 dbg_printf("subxcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd);
01425 int dest = readReg(rs1) - simm13 - PSR_icc_c;
01426
01427 PSR_icc_n = dest >> 31;
01428 PSR_icc_z = dest == 0;
01429 PSR_icc_v = (( readReg(rs1) & ~simm13 & ~dest & 0x80000000) |
01430 (~readReg(rs1) & simm13 & dest & 0x80000000) );
01431 PSR_icc_c = ((~readReg(rs1) & simm13 & 0x80000000) |
01432 (dest & (~readReg(rs1) | simm13) & 0x80000000) );
01433
01434 writeReg(rd, dest);
01435 dbg_printf("Result = 0x%x\n", dest);
01436 update_pc(0,0,0,0,0, ac_pc, npc);
01437 };
01438
01440 void ac_behavior( jmpl_imm )
01441 {
01442 dbg_printf("jmpl_imm r%d,%d,r%d\n", rs1, simm13, rd);
01443 writeReg(rd, ac_pc);
01444 update_pc(1,1,1,0, readReg(rs1) + simm13, ac_pc, npc);
01445 };
01446
01448 void ac_behavior( save_imm )
01449 {
01450 dbg_printf("save_imm r%d, %d, r%d\n", rs1, simm13, rd);
01451 int tmp = readReg(rs1) + simm13;
01452
01453
01454 for (int i=16; i<32; i++) {
01455 RB.write((CWP + i) & 0xFF, REGS[i]);
01456 }
01457
01458
01459 for (int i=0; i<8; i++) {
01460 REGS[i+24] = REGS[i+8];
01461 }
01462
01463
01464 CWP = (CWP-0x10);
01465 if (CWP == WIM) trap_reg_window_overflow(DM, RB, WIM);
01466
01467
01468 for (int i=8; i<24; i++) {
01469 REGS[i] = RB.read((CWP + i) & 0xFF);
01470 }
01471
01472 writeReg(rd, tmp);
01473 dbg_printf(C_INVERSE "CWP: %d" C_RESET LF, CWP>>4);
01474 dbg_printf("Result = 0x%x\n", readReg(rd));
01475 update_pc(0,0,0,0,0, ac_pc, npc);
01476 };
01477
01479 void ac_behavior( restore_imm )
01480 {
01481 dbg_printf("restore_imm r%d, %d, r%d\n", rs1, simm13, rd);
01482 int tmp = readReg(rs1) + simm13;
01483
01484
01485 for (int i=8; i<24; i++) {
01486 RB.write((CWP + i) & 0xFF, REGS[i]);
01487 }
01488
01489
01490 for (int i=0; i<8; i++) {
01491 REGS[i+8] = REGS[i+24];
01492 }
01493
01494
01495 CWP = (CWP+0x10);
01496 if (CWP == WIM) trap_reg_window_underflow(DM, RB, WIM);
01497
01498
01499 for (int i=16; i<32; i++) {
01500 REGS[i] = RB.read((CWP + i) & 0xFF);
01501 }
01502
01503 writeReg(rd, tmp);
01504 dbg_printf(C_INVERSE "CWP: %d" C_RESET LF, CWP>>4);
01505 dbg_printf("Result = 0x%x\n", readReg(rd));
01506 update_pc(0,0,0,0,0, ac_pc, npc);
01507 };
01508
01510 void ac_behavior( rdy )
01511 {
01512 dbg_printf("rdy r%d\n", rd);
01513 writeReg(rd, Y.read());
01514 update_pc(0,0,0,0,0, ac_pc, npc);
01515 };
01516
01518 void ac_behavior( wry_imm )
01519 {
01520 dbg_printf("wry_imm\n");
01521 Y.write( readReg(rs1) ^ simm13);
01522 update_pc(0,0,0,0,0, ac_pc, npc);
01523 };
01524
01526 void ac_behavior( mulscc_reg )
01527 {
01528 dbg_printf("mulscc_reg r%d, r%d, r%d\n", rs1, rs2, rd);
01529 int rs1_0 = readReg(rs1) & 1;
01530 int op1 = ((PSR_icc_n ^ PSR_icc_v) << 31) | (readReg(rs1) >> 1);
01531 int op2 = ((Y.read() & 1) == 0) ? 0 : readReg(rs2);
01532 int dest = op1+op2;
01533
01534 PSR_icc_n = dest >> 31;
01535 PSR_icc_z = dest == 0;
01536 PSR_icc_v = (( op1 & op2 & ~dest & 0x80000000) |
01537 (~op1 & ~op2 & dest & 0x80000000) );
01538 PSR_icc_c = (( op1 & op2 & 0x80000000) |
01539 (~dest & (op1 | op2) & 0x80000000) );
01540
01541 writeReg(rd, dest);
01542 Y.write( (rs1_0 << 31) | (Y.read() >> 1));
01543 update_pc(0,0,0,0,0, ac_pc, npc);
01544 }
01545
01547 void ac_behavior( mulscc_imm )
01548 {
01549 dbg_printf("mulscc_imm r%d, %d, r%d\n", rs1, simm13, rd);
01550 int rs1_0 = readReg(rs1) & 1;
01551 int op1 = ((PSR_icc_n ^ PSR_icc_v) << 31) | (readReg(rs1) >> 1);
01552 int op2 = ((Y.read() & 1) == 0) ? 0 : simm13;
01553 int dest = op1+op2;
01554
01555 PSR_icc_n = dest >> 31;
01556 PSR_icc_z = dest == 0;
01557 PSR_icc_v = (( op1 & op2 & ~dest & 0x80000000) |
01558 (~op1 & ~op2 & dest & 0x80000000) );
01559 PSR_icc_c = (( op1 & op2 & 0x80000000) |
01560 (~dest & (op1 | op2) & 0x80000000) );
01561
01562 writeReg(rd, dest);
01563 Y.write( (rs1_0 << 31) | (Y.read() >> 1));
01564 update_pc(0,0,0,0,0, ac_pc, npc);
01565 }
01566
01568
01569 void ac_behavior( trap_reg )
01570 {
01571 dbg_printf("trap\n");
01572 stop();
01573 }
01574
01576
01577 void ac_behavior( trap_imm )
01578 {
01579 dbg_printf("trap\n");
01580 stop();
01581 }
01582
01584 void ac_behavior( unimplemented )
01585 {
01586 dbg_printf("unimplemented\n");
01587 printf("sparcv8-isa.cpp: program flow reach instruction 'unimplemented' at ac_pc=%#x\n", (int)ac_pc);
01588 stop(EXIT_FAILURE);
01589 update_pc(0,0,0,0,0, ac_pc, npc);
01590 }