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armv5e Architechture Description
armv5e Other Properties
ISA (ac_isa):
Name: armv5e_isa.ac
Type_BBL (ac_format):
Format Description: offset 24; h 1; op 3; cond 4;
Instructions: b
Type_LSR (ac_format):
Format Description: rm 4; subop1 1; shift 2; shiftamount 5; rd 4; rn 4; l 1; w 1; b 1; u 1; p 1; op 3; cond 4;
Instructions: ldr2 strt2 strbt2 ldrt2 strb2 ldrbt2 ldrb2 str2
Type_MBKPT (ac_format):
Format Description: rm 4; subop1 1; func2 2; subop2 1; immediate 12; s 1; func1 4; op 3; cond 4;
Instructions: bkpt
Type_MULT1 (ac_format):
Format Description: rm 4; subop1 1; func2 2; subop2 1; rs 4; rd 4; rn 4; s 1; func1 4; op 3; cond 4;
Instructions: swpb mla mul swp
Type_BBLT (ac_format):
Format Description: offset 24; h 1; op 3; cond 4;
Instructions: blx1
Type_MULT2 (ac_format):
Format Description: rm 4; subop1 1; func2 2; subop2 1; rs 4; rdlo 4; rdhi 4; s 1; func1 4; op 3; cond 4;
Instructions: umlal smull umull smlal
Type_DPI1 (ac_format):
Format Description: rm 4; subop1 1; shift 2; shiftamount 5; rd 4; rn 4; s 1; func1 4; op 3; cond 4;
Instructions: mvn1 adc1 orr1 bic1 cmp1 mov1 eor1 teq1 sbc1 rsc1 tst1 add1 rsb1 and1 cmn1 sub1
Type_DPI3 (ac_format):
Format Description: imm8 8; rotate 4; rd 4; rn 4; s 1; func1 4; op 3; cond 4;
Instructions: mvn3 adc3 orr3 bic3 cmp3 mov3 eor3 sbc3 rsc3 teq3 add3 rsb3 tst3 sub3 and3 cmn3
Type_DPI2 (ac_format):
Format Description: rm 4; subop1 1; shift 2; subop2 1; rs 4; rd 4; rn 4; s 1; func1 4; op 3; cond 4;
Instructions: mvn2 adc2 orr2 mov2 cmp2 bic2 eor2 teq2 sbc2 rsc2 tst2 add2 rsb2 and2 cmn2 sub2
Type_MSWI (ac_format):
Format Description: swinumber 24; subop3 1; op 3; cond 4;
Instructions: swi
Type_MMSR1 (ac_format):
Format Description: rm 4; subop1 1; func2 2; subop2 1; zero3 4; rd 4; field 4; func12 2; r 1; func11 2; op 3; cond 4;
Instructions: msr1 mrs
Type_MMSR2 (ac_format):
Format Description: imm8 8; rotate 4; one2 4; field 4; func12 2; r 1; func11 2; op 3; cond 4;
Instructions: msr2
Type_CLS (ac_format):
Format Description: imm8 8; cp_num 4; crd 4; rn 4; l 1; w 1; n 1; u 1; p 1; op 3; cond 4;
Instructions: ldc stc
Type_LSE (ac_format):
Format Description: addr2 4; subop1 1; hh 1; ss 1; subop2 1; addr1 4; rd 4; rn 4; l 1; w 1; i 1; u 1; p 1; op 3; cond 4;
Instructions: ldrd ldrh ldrsh ldrsb strh strd
Type_MBXBLX (ac_format):
Format Description: rm 4; subop1 1; func2 2; subop2 1; one3 4; one2 4; one1 4; s 1; func1 4; op 3; cond 4;
Instructions: bx blx2
Type_LSI (ac_format):
Format Description: imm12 12; rd 4; rn 4; l 1; w 1; b 1; u 1; p 1; op 3; cond 4;
Instructions: ldr1 strt1 strbt1 ldrt1 strb1 ldrbt1 ldrb1 str1
Type_CDP (ac_format):
Format Description: crm 4; subop1 1; funcc3 3; cp_num 4; crd 4; crn 4; funcc1 4; subop3 1; op 3; cond 4;
Instructions: cdp
Type_MCLZ (ac_format):
Format Description: rm 4; subop1 1; func2 2; subop2 1; one3 4; rd 4; one1 4; s 1; func1 4; op 3; cond 4;
Instructions: clz
Type_CRT (ac_format):
Format Description: crm 4; subop1 1; funcc3 3; cp_num 4; rd 4; crn 4; l 1; funcc2 3; subop3 1; op 3; cond 4;
Instructions: mcr mrc
Type_LSM (ac_format):
Format Description: rlist 16; rn 4; l 1; w 1; r 1; u 1; p 1; op 3; cond 4;
Instructions: ldm stm
Type_DSPSM (ac_format):
Format Description: rm 4; subop1 1; xx 1; yy 1; subop2 1; rs 4; drn 4; drd 4; sm 8; cond 4;
Instructions: dsmul dsmla dsmulw dsmlaw dsmlal
mvn3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=15;
ASM: mvn %cond %s %rd, %rn, %imm8
mvn2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=15;
ASM: mvn %cond %s %rd, %rn, %rm, %shift %rs
mvn1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=15;
ASM: mvn %cond %s %rd, %rn, %rm, %shift %shiftamount
dsmul (ac_instr):
Instruction Type: Type_DSPSM
Decoder: sm=22; subop2=1; subop1=0;
ASM:
ldm (ac_instr):
Instruction Type: Type_LSM
Decoder: op=4; l=1;
ASM: ldm %cond %p %u %w %rn %w, %rlist
dsmla (ac_instr):
Instruction Type: Type_DSPSM
Decoder: sm=16; subop2=1; subop1=0;
ASM:
adc2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=5;
ASM: adc %cond %s %rd, %rn, %rm, %shift %rs
adc3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=5;
ASM: adc %cond %s %rd, %rn, %imm8
adc1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=5;
ASM: adc %cond %s %rd, %rn, %rm, %shift %shiftamount
orr1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=12;
ASM: orr %cond %s %rd, %rn, %rm, %shift %shiftamount
orr3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=12;
ASM: orr %cond %s %rd, %rn, %imm8
orr2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=12;
ASM: orr %cond %s %rd, %rn, %rm, %shift %rs
mov2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=13;
ASM: mov %cond %s %rd, %rn, %rm, %shift %rs
bic3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=14;
ASM: bic %cond %s %rd, %rn, %imm8
clz (ac_instr):
Instruction Type: Type_MCLZ
Decoder: op=0; subop1=1; subop2=0; func1=11; func2=0; s=0;
ASM: clz %cond %rm %rd
bic1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=14;
ASM: bic %cond %s %rd, %rn, %rm, %shift %shiftamount
cmp1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=10; s=1;
ASM: cmp %cond %rd, %rn, %rm, %shift %shiftamount
cmp2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=10; s=1;
ASM: cmp %cond %rd, %rn, %rm, %shift %rs
cmp3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=10; s=1;
ASM: cmp %cond %rd, %rn, %imm8
umlal (ac_instr):
Instruction Type: Type_MULT2
Decoder: op=0; subop1=1; subop2=1; func1=5; func2=0;
ASM: umlal %cond %s %rdlo, %rdhi, %rm, %rs
swpb (ac_instr):
Instruction Type: Type_MULT1
Decoder: op=0; subop1=1; subop2=1; func1=10; func2=0; s=0;
ASM: swpb %cond %rd, %rm, %rn
mla (ac_instr):
Instruction Type: Type_MULT1
Decoder: op=0; subop1=1; subop2=1; func1=1; func2=0;
ASM: mla %cond %s, %rd, %rm, %rs, %rn
bic2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=14;
ASM: bic %cond %s %rd, %rn, %rm, %shift %rs
mov3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=13;
ASM: mov %cond %s %rd, %rn, %imm8
mov1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=13;
ASM: mov %cond %s %rd, %rn, %rm, %shift %shiftamount
eor2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=1;
ASM: eor %cond %s %rd, %rn, %rm, %shift %rs
eor3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=1;
ASM: eor %cond %s %rd, %rn, %imm8
eor1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=1;
ASM: eor %cond %s %rd, %rn, %rm, %shift %shiftamount
ldc (ac_instr):
Instruction Type: Type_CLS
Decoder: op=6; l=1;
ASM: ldc %cond %l %cp_num, %crd, %imm8
teq2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=9; s=1;
ASM: teq %cond %rd, %rn, %rm, %shift %rs
cdp (ac_instr):
Instruction Type: Type_CDP
Decoder: op=7; subop1=0; subop3=0;
ASM: cdp %cond %cp_num, %funcc1, %crd, %crn, %crm %funcc3
teq1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=9; s=1;
ASM: teq %cond %rd, %rn, %rm, %shift %shiftamount
ldr2 (ac_instr):
Instruction Type: Type_LSR
Decoder: op=3; subop1=0; b=0; l=1;
ASM: ldr %cond %rd, %rn, %rm, %shift %shiftamount %w
ldr1 (ac_instr):
Instruction Type: Type_LSI
Decoder: op=2; b=0; l=1;
ASM: ldr %cond %rd, %rn, %imm12 %w
smull (ac_instr):
Instruction Type: Type_MULT2
Decoder: op=0; subop1=1; subop2=1; func1=6; func2=0;
ASM: smull %cond %s %rdlo, %rdhi, %rm, %rs
strt1 (ac_instr):
Instruction Type: Type_LSI
Decoder: op=2; p=0; b=0; w=1; l=0;
ASM: strt %cond %rd, %rn, %imm12 %w
strt2 (ac_instr):
Instruction Type: Type_LSR
Decoder: op=3; subop1=0; p=0; b=0; w=1; l=0;
ASM: strt %cond %rd, %rn, %rm, %shift %shiftamount %w
dsmulw (ac_instr):
Instruction Type: Type_DSPSM
Decoder: sm=18; subop2=1; xx=1; subop1=0;
ASM:
mul (ac_instr):
Instruction Type: Type_MULT1
Decoder: op=0; subop1=1; subop2=1; func1=0; func2=0;
ASM: mul %cond %s, %rd, %rm, %rs
strbt2 (ac_instr):
Instruction Type: Type_LSR
Decoder: op=3; subop1=0; p=0; b=1; w=1; l=0;
ASM: strbt %cond %rd, %rn, %rm, %shift %shiftamount %w
strbt1 (ac_instr):
Instruction Type: Type_LSI
Decoder: op=2; p=0; b=1; w=1; l=0;
ASM: strbt %cond %rd, %rn, %imm12 %w
sbc2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=6;
ASM: sbc %cond %s %rd, %rn, %rm, %shift %rs
sbc3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=6;
ASM: sbc %cond %s %rd, %rn, %imm8
sbc1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=6;
ASM: sbc %cond %s %rd, %rn, %rm, %shift %shiftamount
rsc1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=7;
ASM: rsc %cond %s %rd, %rn, %rm, %shift %shiftamount
rsc2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=7;
ASM: rsc %cond %s %rd, %rn, %rm, %shift %rs
rsc3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=7;
ASM: rsc %cond %s %rd, %rn, %imm8
ldrd (ac_instr):
Instruction Type: Type_LSE
Decoder: op=0; subop1=1; subop2=1; ss=1; hh=0; l=0;
ASM: ldrd %cond %rd, %addr1 %addr2
teq3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=9; s=1;
ASM: teq %cond %rd, %rn, %imm8
ldrh (ac_instr):
Instruction Type: Type_LSE
Decoder: op=0; subop1=1; subop2=1; ss=0; hh=1; l=1;
ASM: ldrh %cond %rd, %addr1 %addr2
bx (ac_instr):
Instruction Type: Type_MBXBLX
Decoder: op=0; subop1=1; subop2=0; func1=9; s=0; func2=0;
ASM: bx %cond %rm
tst2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=8; s=1;
ASM: tst %cond %rd, %rn, %rm, %shift %rs
tst1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=8; s=1;
ASM: tst %cond %rd, %rn, %rm, %shift %shiftamount
add3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=4;
ASM: add %cond %s %rd, %rn, %imm8
add2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=4;
ASM: add %cond %s %rd, %rn, %rm, %shift %rs
add1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=4;
ASM: add %cond %s %rd, %rn, %rm, %shift %shiftamount
ldrt2 (ac_instr):
Instruction Type: Type_LSR
Decoder: op=3; subop1=0; p=0; b=0; w=1; l=1;
ASM: ldrt %cond %rd, %rn, %rm, %shift %shiftamount %w
ldrt1 (ac_instr):
Instruction Type: Type_LSI
Decoder: op=2; p=0; b=0; w=1; l=1;
ASM: ldrt %cond %rd, %rn, %imm12 %w
strb2 (ac_instr):
Instruction Type: Type_LSR
Decoder: op=3; subop1=0; b=1; l=0;
ASM: strb %cond %rd, %rn, %rm, %shift %shiftamount %w
strb1 (ac_instr):
Instruction Type: Type_LSI
Decoder: op=2; b=1; l=0;
ASM: strb %cond %rd, %rn, %imm12 %w
dsmlaw (ac_instr):
Instruction Type: Type_DSPSM
Decoder: sm=18; subop2=1; xx=0; subop1=0;
ASM:
rsb3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=3;
ASM: rsb %cond %s %rd, %rn, %imm8
rsb2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=3;
ASM: rsb %cond %s %rd, %rn, %rm, %shift %rs
rsb1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=3;
ASM: rsb %cond %s %rd, %rn, %rm, %shift %shiftamount
dsmlal (ac_instr):
Instruction Type: Type_DSPSM
Decoder: sm=20; subop2=1; subop1=0;
ASM:
swi (ac_instr):
Instruction Type: Type_MSWI
Decoder: op=7; subop3=1;
ASM: swi %cond %swinumber
tst3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=8; s=1;
ASM: tst %cond %rd, %rn, %imm8
ldrbt2 (ac_instr):
Instruction Type: Type_LSR
Decoder: op=3; subop1=0; p=0; b=1; w=1; l=1;
ASM: ldrbt %cond %rd, %rn, %rm, %shift %shiftamount %w
ldrbt1 (ac_instr):
Instruction Type: Type_LSI
Decoder: op=2; p=0; b=1; w=1; l=1;
ASM: ldrbt %cond %rd, %rn, %imm12 %w
bkpt (ac_instr):
Instruction Type: Type_MBKPT
Decoder: op=0; subop1=1; subop2=0; func1=9; func2=3; s=0; cond=14;
ASM: bkpt %immediate
swp (ac_instr):
Instruction Type: Type_MULT1
Decoder: op=0; subop1=1; subop2=1; func1=8; func2=0; s=0;
ASM: swp %cond %rd, %rm, %rn
msr2 (ac_instr):
Instruction Type: Type_MMSR2
Decoder: op=1; func11=2; func12=2;
ASM: msr %cond %field, %imm8
msr1 (ac_instr):
Instruction Type: Type_MMSR1
Decoder: op=0; subop1=0; subop2=0; func11=2; func12=2;
ASM: msr %cond %field, %rm
blx2 (ac_instr):
Instruction Type: Type_MBXBLX
Decoder: op=0; subop1=1; subop2=0; func1=9; s=0; func2=1;
ASM: blx %cond %rm
sub3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=2;
ASM: sub %cond %s %rd, %rn, %imm8
blx1 (ac_instr):
Instruction Type: Type_BBLT
Decoder: op=5; cond=15;
ASM: blx %offset
ldrb1 (ac_instr):
Instruction Type: Type_LSI
Decoder: op=2; b=1; l=1;
ASM: ldrb %cond %rd, %rn, %imm12 %w
ldrb2 (ac_instr):
Instruction Type: Type_LSR
Decoder: op=3; subop1=0; b=1; l=1;
ASM: ldrb %cond %rd, %rn, %rm, %shift %shiftamount %w
mcr (ac_instr):
Instruction Type: Type_CRT
Decoder: op=7; subop1=1; subop3=0; l=0;
ASM: mcr %cond %cp_num, %funcc2, %rd, %crn, %crm, %funcc3
b (ac_instr):
Instruction Type: Type_BBL
Decoder: op=5;
ASM: b %h %cond %offset
stc (ac_instr):
Instruction Type: Type_CLS
Decoder: op=6; l=0;
ASM: stc %cond %l %cp_num, %crd, %imm8 %w
stm (ac_instr):
Instruction Type: Type_LSM
Decoder: op=4; l=0;
ASM: stm %cond %p %u %w %rn %w, %rlist
and1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=0;
ASM: and %cond %s %rd, %rn, %rm, %shift %shiftamount
and3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=0;
ASM: and %cond %s %rd, %rn, %imm8
and2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=0;
ASM: and %cond %s %rd, %rn, %rm, %shift %rs
cmn2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=11; s=1;
ASM: cmn %cond %rd, %rn, %rm, %shift %rs
cmn3 (ac_instr):
Instruction Type: Type_DPI3
Decoder: op=1; func1=11; s=1;
ASM: cmn %cond %rd, %rn, %imm8
cmn1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=11; s=1;
ASM: cmn %cond %rd, %rn, %rm, %shift %shiftamount
sub2 (ac_instr):
Instruction Type: Type_DPI2
Decoder: op=0; subop1=1; subop2=0; func1=2;
ASM: sub %cond %s %rd, %rn, %rm, %shift %rs
str2 (ac_instr):
Instruction Type: Type_LSR
Decoder: op=3; subop1=0; b=0; l=0;
ASM: str %cond %rd, %rn, %rm, %shift %shiftamount %w
str1 (ac_instr):
Instruction Type: Type_LSI
Decoder: op=2; b=0; l=0;
ASM: str %cond %rd, %rn, %imm12 %w
sub1 (ac_instr):
Instruction Type: Type_DPI1
Decoder: op=0; subop1=0; func1=2;
ASM: sub %cond %s %rd, %rn, %rm, %shift %shiftamount
ldrsh (ac_instr):
Instruction Type: Type_LSE
Decoder: op=0; subop1=1; subop2=1; ss=1; hh=1; l=1;
ASM: ldrsh %cond %rd, %addr1 %addr2
umull (ac_instr):
Instruction Type: Type_MULT2
Decoder: op=0; subop1=1; subop2=1; func1=4; func2=0;
ASM: umull %cond %s %rdlo, %rdhi, %rm, %rs
ldrsb (ac_instr):
Instruction Type: Type_LSE
Decoder: op=0; subop1=1; subop2=1; ss=1; hh=0; l=1;
ASM: ldrsb %cond %rd, %addr1 %addr2
mrs (ac_instr):
Instruction Type: Type_MMSR1
Decoder: op=0; subop1=0; subop2=0; func11=2; func12=0;
ASM: mrs %cond %rn, %r
strh (ac_instr):
Instruction Type: Type_LSE
Decoder: op=0; subop1=1; subop2=1; ss=0; hh=1; l=0;
ASM: strh %cond %rd, %addr1 %addr2
smlal (ac_instr):
Instruction Type: Type_MULT2
Decoder: op=0; subop1=1; subop2=1; func1=7; func2=0;
ASM: smlal %cond %s %rdlo, %rdhi, %rm, %rs
mrc (ac_instr):
Instruction Type: Type_CRT
Decoder: op=7; subop1=1; subop3=0; l=1;
ASM: mrc %cond %cp_num, %funcc2, %rd, %crn, %crm, %funcc3
strd (ac_instr):
Instruction Type: Type_LSE
Decoder: op=0; subop1=1; subop2=1; ss=1; hh=1; l=0;
ASM: strd %cond %rd, %addr1 %addr2