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- 00001     /**
- 00002     * @file sparcv8_isa.ac
- 00003     * @author Sandro Rigo
- 00004     * Marcus Bartholomeu
- 00005     * Alexandro Baldassin (assembly information)
- 00006     *
- 00007     * The ArchC Team
- 00008     * http://www.archc.org/
- 00009     *
- 00010     * Computer Systems Laboratory (LSC)
- 00011     * IC-UNICAMP
- 00012     * http://www.lsc.ic.unicamp.br
- 00013     *
- 00014     * @version 1.0
- 00015     * @date Thu, 29 Jun 2006 14:49:07 -0300
- 00016     *
- 00017     * @brief The ArchC SPARC-V8 functional model.
- 00018     *
- 00019     * @attention Copyright (C) 2002-2006 --- The ArchC Team
- 00020     *
- 00021     */
- 00022    
- 00023     AC_ISA (sparcv8){
- 00024    
- 00025     ac_format Type_F1 = "%op:2 %disp30:30" ;
- 00026     ac_format Type_F2A = "%op:2 %rd:5 %op2:3 %imm22:22" ;
- 00027     ac_format Type_F2B = "%op:2 %an:1 %cond :4 %op2:3 %disp22:22:s" ;
- 00028     ac_format Type_F3A = "%op:2 %rd:5 %op3:6 %rs1:5 %is:1 %asi:8 %rs2:5" ;
- 00029     ac_format Type_F3B = "%op:2 %rd:5 %op3:6 %rs1:5 %is:1 %simm13:13:s" ;
- 00030     /* format for trap instructions */
- 00031     ac_format Type_FT = "%op:2 %r1:1 %cond :4 %op2a:6 %rs1:5 %is:1 [%r2a:8 %rs2:5 | %r2b:6 %imm7:7]" ;
- 00032    
- 00033     ac_instr call;
- 00034     ac_instr nop, sethi;
- 00035     ac_instr ba, bn, bne, be, bg, ble, bge, bl, bgu, bleu, bcc, bcs,
- 00036     bpos, bneg, bvc, bvs;
- 00037    
- 00038     ac_instr ldsb_reg, ldsh_reg, ldub_reg, lduh_reg, ld_reg, ldd_reg,
- 00039     stb_reg, sth_reg, st_reg, std_reg, ldstub_reg, swap_reg,
- 00040     sll_reg, srl_reg, sra_reg, add_reg, addcc_reg, addx_reg,
- 00041     addxcc_reg, sub_reg, subcc_reg, subx_reg, subxcc_reg,
- 00042     and_reg, andcc_reg, andn_reg, andncc_reg, or_reg, orcc_reg,
- 00043     orn_reg, orncc_reg, xor_reg, xorcc_reg, xnor_reg,
- 00044     xnorcc_reg, save_reg, restore_reg, umul_reg, smul_reg,
- 00045     umulcc_reg, smulcc_reg, mulscc_reg, udiv_reg, udivcc_reg,
- 00046     sdiv_reg, sdivcc_reg, jmpl_reg, wry_reg;
- 00047    
- 00048     ac_instr ldsb_imm, ldsh_imm, ldub_imm, lduh_imm, ld_imm, ldd_imm,
- 00049     and_imm, andcc_imm, andn_imm, andncc_imm, or_imm, orcc_imm,
- 00050     orn_imm, orncc_imm, xor_imm, xorcc_imm, xnor_imm,
- 00051     xnorcc_imm, umul_imm, smul_imm, umulcc_imm, smulcc_imm,
- 00052     mulscc_imm, udiv_imm, udivcc_imm, sdiv_imm, sdivcc_imm;
- 00053    
- 00054     ac_instr stb_imm, sth_imm, st_imm, std_imm, ldstub_imm, swap_imm,
- 00055     sll_imm, srl_imm, sra_imm, add_imm, addcc_imm, addx_imm,
- 00056     addxcc_imm, sub_imm, subcc_imm, subx_imm, subxcc_imm,
- 00057     jmpl_imm, save_imm, restore_imm, rdy, wry_imm;
- 00058    
- 00059     ac_instr unimplemented;
- 00060     ac_instr trap_reg, trap_imm;
- 00061    
- 00062    
- 00063     ac_asm_map reg {
- 00064     "%r" [0..31] = [0..31];
- 00065     "%g" [0..7] = [0..7];
- 00066     "%o" [0..7] = [8..15];
- 00067     "%l" [0..7] = [16..23];
- 00068     "%i" [0..7] = [24..31];
- 00069     "%fp" = 30;
- 00070     "%sp" = 14;
- 00071     }
- 00072    
- 00073     ac_asm_map anul {
- 00074     "" = 0;
- 00075     ",a" = 1;
- 00076     }
- 00077    
- 00078     ac_asm_map cond {
- 00079     "a" = 8;
- 00080     "n" = 0;
- 00081     "ne" = 5;
- 00082     "e" = 1;
- 00083     "g" = 10;
- 00084     "le" = 2;
- 00085     "ge" = 11;
- 00086     "l" = 3;
- 00087     "gu" = 12;
- 00088     "leu" = 4;
- 00089     "cc" = 13;
- 00090     "cs" = 5;
- 00091     "pos" = 14;
- 00092     "neg" = 6;
- 00093     "vc" = 15;
- 00094     "vs" = 7;
- 00095     }
- 00096    
- 00097    
- 00098     ISA_CTOR (sparcv8){
- 00099    
- 00100     ldsb_reg.set_asm ("ldsb [%reg + %reg], %reg" , rs1, rs2, rd);
- 00101     ldsb_reg.set_asm ("ldsb [%reg], %reg" , rs1, rd, rs2="%g0");
- 00102     ldsb_reg.set_decoder (op=0x03, op3=0x09, is=0x00);
- 00103    
- 00104     ldsh_reg.set_asm ("ldsh [%reg + %reg], %reg" , rs1, rs2, rd);
- 00105     ldsh_reg.set_asm ("ldsh [%reg], %reg" , rs1, rd, rs2="%g0");
- 00106     ldsh_reg.set_decoder (op=0x03, op3=0x0A, is=0x00);
- 00107    
- 00108     ldub_reg.set_asm ("ldub [%reg + %reg], %reg" , rs1, rs2, rd);
- 00109     ldub_reg.set_asm ("ldub [%reg], %reg" , rs1, rd, rs2="%g0");
- 00110     ldub_reg.set_decoder (op=0x03, op3=0x01, is=0x00);
- 00111    
- 00112     lduh_reg.set_asm ("lduh [%reg + %reg], %reg" , rs1, rs2, rd);
- 00113     lduh_reg.set_asm ("lduh [%reg], %reg" , rs1, rd, rs2="%g0");
- 00114     lduh_reg.set_decoder (op=0x03, op3=0x02, is=0x00);
- 00115    
- 00116     ld_reg.set_asm ("ld [%reg + %reg], %reg" , rs1, rs2, rd);
- 00117     ld_reg.set_asm ("ld [%reg], %reg" , rs1, rd, rs2="%g0");
- 00118     ld_reg.set_decoder (op=0x03, op3=0x00, is=0x00);
- 00119    
- 00120     ldd_reg.set_asm ("ldd [%reg + %reg], %reg" , rs1, rs2, rd);
- 00121     ldd_reg.set_asm ("ldd [%reg], %reg" , rs1, rd, rs2="%g0");
- 00122     ldd_reg.set_decoder (op=0x03, op3=0x03, is=0x00);
- 00123    
- 00124     stb_reg.set_asm ("stb %reg, [%reg + %reg]" , rd, rs1, rs2);
- 00125     stb_reg.set_asm ("stb %reg, [%reg]" , rd, rs1, rs2="%g0");
- 00126     stb_reg.set_asm ("clrb [%reg + %reg]" , rd="%g0", rs1, rs2); // synthetic
- 00127     stb_reg.set_asm ("clrb [%reg]" , rd="%g0", rs1, rs2="%g0"); // synthetic
- 00128     stb_reg.set_decoder (op=0x03, op3=0x05, is=0x00);
- 00129    
- 00130     sth_reg.set_asm ("sth %reg, [%reg + %reg]" , rd, rs1, rs2);
- 00131     sth_reg.set_asm ("sth %reg, [%reg]" , rd, rs1, rs2="%g0");
- 00132     sth_reg.set_asm ("clrh [%reg + %reg]" , rd="%g0", rs1, rs2); // synthetic
- 00133     sth_reg.set_asm ("clrh [%reg]" , rd="%g0", rs1, rs2="%g0"); // synthetic
- 00134     sth_reg.set_decoder (op=0x03, op3=0x06, is=0x00);
- 00135    
- 00136     st_reg.set_asm ("st %reg, [%reg + %reg]" , rd, rs1, rs2);
- 00137     st_reg.set_asm ("st %reg, [%reg]" , rd, rs1, rs2="%g0");
- 00138     st_reg.set_asm ("clr [%reg + %reg]" , rd="%g0", rs1, rs2); // synthetic
- 00139     st_reg.set_asm ("clr [%reg]" , rd="%g0", rs1, rs2="%g0"); // synthetic
- 00140     st_reg.set_decoder (op=0x03, op3=0x04, is=0x00);
- 00141    
- 00142     std_reg.set_asm ("std %reg, [%reg + %reg]" , rd, rs1, rs2);
- 00143     std_reg.set_asm ("std %reg, [%reg]" , rd, rs1, rs2="%g0");
- 00144     std_reg.set_decoder (op=0x03, op3=0x07, is=0x00);
- 00145    
- 00146     ldstub_reg.set_asm ("ldstub [%reg + %reg], %reg" , rs1, rs2, rd);
- 00147     ldstub_reg.set_asm ("ldstub [%reg], %reg" , rs1, rd, rs2="%g0");
- 00148     ldstub_reg.set_decoder (op=0x03, op3=0x0D, is=0x00);
- 00149    
- 00150     swap_reg.set_asm ("swap [%reg + %reg], %reg" , rs1, rs2, rd);
- 00151     swap_reg.set_asm ("swap [%reg], %reg" , rs1, rd, rs2="%g0");
- 00152     swap_reg.set_decoder (op=0x03, op3=0x0F, is=0x00);
- 00153    
- 00154     ldsb_imm.set_asm ("ldsb [%reg + \%lo(%exp(low))], %reg" , rs1, simm13, rd);
- 00155     ldsb_imm.set_asm ("ldsb [%reg + %imm], %reg" , rs1, simm13, rd);
- 00156     ldsb_imm.set_asm ("ldsb [%imm + %reg], %reg" , simm13, rs1, rd);
- 00157     ldsb_imm.set_asm ("ldsb [%imm], %reg" , simm13, rd, rs1="%g0");
- 00158     ldsb_imm.set_decoder (op=0x03, op3=0x09, is = 0x01);
- 00159    
- 00160     ldsh_imm.set_asm ("ldsh [%reg + \%lo(%exp(low))], %reg" , rs1, simm13, rd);
- 00161     ldsh_imm.set_asm ("ldsh [%reg + %imm], %reg" , rs1, simm13, rd);
- 00162     ldsh_imm.set_asm ("ldsh [%imm + %reg], %reg" , simm13, rs1, rd);
- 00163     ldsh_imm.set_asm ("ldsh [%imm], %reg" , simm13, rd, rs1="%g0");
- 00164     ldsh_imm.set_decoder (op=0x03, op3=0x0A, is = 0x01);
- 00165    
- 00166     ldub_imm.set_asm ("ldub [%reg + \%lo(%exp(low))], %reg" , rs1, simm13, rd);
- 00167     ldub_imm.set_asm ("ldub [%reg + %imm], %reg" , rs1, simm13, rd);
- 00168     ldub_imm.set_asm ("ldub [%imm + %reg], %reg" , simm13, rs1, rd);
- 00169     ldub_imm.set_asm ("ldub [%imm], %reg" , simm13, rd, rs1="%g0");
- 00170     ldub_imm.set_decoder (op=0x03, op3=0x01, is = 0x01);
- 00171    
- 00172     lduh_imm.set_asm ("lduh [%reg + \%lo(%exp(low))], %reg" , rs1, simm13, rd);
- 00173     lduh_imm.set_asm ("lduh [%reg + %imm], %reg" , rs1, simm13, rd);
- 00174     lduh_imm.set_asm ("lduh [%imm + %reg], %reg" , simm13, rs1, rd);
- 00175     lduh_imm.set_asm ("lduh [%imm], %reg" , simm13, rd, rs1="%g0");
- 00176     lduh_imm.set_decoder (op=0x03, op3=0x02, is = 0x01);
- 00177    
- 00178     ld_imm.set_asm ("ld [%reg + \%lo(%exp(low))], %reg" , rs1, simm13, rd);
- 00179     ld_imm.set_asm ("ld [%reg + %imm], %reg" , rs1, simm13, rd);
- 00180     ld_imm.set_asm ("ld [%imm + %reg], %reg" , simm13, rs1, rd);
- 00181     ld_imm.set_asm ("ld [%imm], %reg" , simm13, rd, rs1="%g0");
- 00182     ld_imm.set_decoder (op=0x03, op3=0x00, is = 0x01);
- 00183    
- 00184     ldd_imm.set_asm ("ldd [%reg + \%lo(%exp(low))], %reg" , rs1, simm13, rd);
- 00185     ldd_imm.set_asm ("ldd [%reg + %imm], %reg" , rs1, simm13, rd);
- 00186     ldd_imm.set_asm ("ldd [%imm + %reg], %reg" , simm13, rs1, rd);
- 00187     ldd_imm.set_asm ("ldd [%imm], %reg" , simm13, rd, rs1="%g0");
- 00188     ldd_imm.set_decoder (op=0x03, op3=0x03, is = 0x01);
- 00189    
- 00190     stb_imm.set_asm ("stb %reg, [%reg + \%lo(%exp(low))]" , rd, rs1, simm13);
- 00191     stb_imm.set_asm ("stb %reg, [%reg + %imm]" , rd, rs1, simm13);
- 00192     stb_imm.set_asm ("stb %reg, [%imm + %reg]" , rd, simm13, rs1);
- 00193     stb_imm.set_asm ("stb %reg, [%imm]" , rd, simm13, rs1="%g0");
- 00194     stb_imm.set_asm ("clrb [%reg + %imm]" , rd="%g0", rs1, simm13); // synthetic
- 00195     stb_imm.set_asm ("clrb [%imm + %reg]" , rd="%g0", simm13, rs1); // synthetic
- 00196     stb_imm.set_asm ("clrb [%imm]" , rd="%g0", rs1="%g0", simm13); // synthetic
- 00197     stb_imm.set_decoder (op=0x03, op3=0x05, is = 0x01);
- 00198    
- 00199     sth_imm.set_asm ("sth %reg, [%reg + \%lo(%exp(low))]" , rd, rs1, simm13);
- 00200     sth_imm.set_asm ("sth %reg, [%reg + %imm]" , rd, rs1, simm13);
- 00201     sth_imm.set_asm ("sth %reg, [%imm + %reg]" , rd, simm13, rs1);
- 00202     sth_imm.set_asm ("sth %reg, [%imm]" , rd, simm13, rs1="%g0");
- 00203     sth_imm.set_asm ("clrh [%reg + %imm]" , rd="%g0", rs1, simm13); // synthetic
- 00204     sth_imm.set_asm ("clrh [%imm + %reg]" , rd="%g0", simm13, rs1); // synthetic
- 00205     sth_imm.set_asm ("clrh [%imm]" , rd="%g0", rs1="%g0", simm13); // synthetic
- 00206     sth_imm.set_decoder (op=0x03, op3=0x06, is = 0x01);
- 00207    
- 00208     st_imm.set_asm ("st %reg, [%reg + \%lo(%exp(low))]" , rd, rs1, simm13);
- 00209     st_imm.set_asm ("st %reg, [%reg + %imm]" , rd, rs1, simm13);
- 00210     st_imm.set_asm ("st %reg, [%imm + %reg]" , rd, simm13, rs1);
- 00211     st_imm.set_asm ("st %reg, [%imm]" , rd, simm13, rs1="%g0");
- 00212     st_imm.set_asm ("clr [%reg + %imm]" , rd="%g0", rs1, simm13); // synthetic
- 00213     st_imm.set_asm ("clr [%imm + %reg]" , rd="%g0", simm13, rs1); // synthetic
- 00214     st_imm.set_asm ("clr [%imm]" , rd="%g0", rs1="%g0", simm13); // synthetic
- 00215     st_imm.set_decoder (op=0x03, op3=0x04, is = 0x01);
- 00216    
- 00217     std_imm.set_asm ("std %reg, [%reg + \%lo(%exp(low))]" , rd, rs1, simm13);
- 00218     std_imm.set_asm ("std %reg, [%reg + %imm]" , rd, rs1, simm13);
- 00219     std_imm.set_asm ("std %reg, [%imm + %reg]" , rd, simm13, rs1);
- 00220     std_imm.set_asm ("std %reg, [%imm]" , rd, simm13, rs1="%g0");
- 00221     std_imm.set_decoder (op=0x03, op3=0x07, is = 0x01);
- 00222    
- 00223     ldstub_imm.set_asm ("ldstub [%reg + \%lo(%exp(low))], %reg" , rs1, simm13, rd);
- 00224     ldstub_imm.set_asm ("ldstub [%reg + %imm], %reg" , rs1, simm13, rd);
- 00225     ldstub_imm.set_asm ("ldstub [%imm + %reg], %reg" , simm13, rs1, rd);
- 00226     ldstub_imm.set_asm ("ldstub [%imm], %reg" , simm13, rd, rs1="%g0");
- 00227     ldstub_imm.set_decoder (op=0x03, op3=0x0D, is = 0x01);
- 00228    
- 00229     swap_imm.set_asm ("swap [%reg + \%lo(%exp(low))], %reg" , rs1, simm13, rd);
- 00230     swap_imm.set_asm ("swap [%reg + %imm], %reg" , rs1, simm13, rd);
- 00231     swap_imm.set_asm ("swap [%imm + %reg], %reg" , simm13, rs1, rd);
- 00232     swap_imm.set_asm ("swap [%imm], %reg" , simm13, rd, rs1="%g0");
- 00233     swap_imm.set_decoder (op=0x03, op3=0x0F, is = 0x01);
- 00234    
- 00235     nop.set_asm ("nop" );
- 00236     nop.set_decoder (op=0x00, rd=0x00, op2=0x04, imm22=0x00);
- 00237    
- 00238     sethi.set_asm ("sethi %exp, %reg" , imm22, rd);
- 00239     sethi.set_asm ("sethi \%hi(%exp(high)), %reg" , imm22, rd);
- 00240     sethi.set_decoder (op=0x00, op2=0x04);
- 00241    
- 00242     and_reg.set_asm ("and %reg, %reg, %reg" , rs1, rs2, rd);
- 00243     and_reg.set_decoder (op=0x02, op3=0x01, is=0x00);
- 00244    
- 00245     and_imm.set_asm ("and %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00246     and_imm.set_asm ("and %reg, %imm, %reg" , rs1, simm13, rd);
- 00247     and_imm.set_decoder (op=0x02, op3=0x01, is=0x01);
- 00248    
- 00249     andcc_reg.set_asm ("andcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00250     andcc_reg.set_asm ("btst %reg, %reg" , rs2, rs1, rd="%g0");
- 00251     andcc_reg.set_decoder (op=0x02, op3=0x11, is=0x00);
- 00252    
- 00253     andcc_imm.set_asm ("andcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00254     andcc_imm.set_asm ("andcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00255     andcc_imm.set_asm ("btst %imm, %reg" , simm13, rs1, rd="%g0");
- 00256     andcc_imm.set_decoder (op=0x02, op3=0x11, is=0x01);
- 00257    
- 00258     andn_reg.set_asm ("andn %reg, %reg, %reg" , rs1, rs2, rd);
- 00259     andn_reg.set_decoder (op=0x02, op3=0x05, is=0x00);
- 00260    
- 00261     andn_imm.set_asm ("andn %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00262     andn_imm.set_asm ("andn %reg, %imm, %reg" , rs1, simm13, rd);
- 00263     andn_imm.set_decoder (op=0x02, op3=0x05, is=0x01);
- 00264    
- 00265     andncc_reg.set_asm ("andncc %reg, %reg, %reg" , rs1, rs2, rd);
- 00266     andncc_reg.set_decoder (op=0x02, op3=0x15, is=0x00);
- 00267    
- 00268     andncc_imm.set_asm ("andncc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00269     andncc_imm.set_asm ("andncc %reg, %imm, %reg" , rs1, simm13, rd);
- 00270     andncc_imm.set_decoder (op=0x02, op3=0x15, is=0x01);
- 00271    
- 00272     or_reg.set_asm ("or %reg, %reg, %reg" , rs1, rs2, rd);
- 00273     or_reg.set_asm ("clr %reg" , rs1="%g0", rs2="%g0", rd); // synthetic
- 00274     or_reg.set_asm ("mov %reg, %reg" , rs1="%g0", rs2, rd); // synthetic
- 00275     or_reg.set_decoder (op=0x02, op3=0x02, is=0x00);
- 00276    
- 00277     or_imm.set_asm ("or %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00278     or_imm.set_asm ("or %reg, %imm, %reg" , rs1, simm13, rd);
- 00279     or_imm.set_asm ("mov %imm, %reg" , rs1="%g0", simm13, rd); // synthetic
- 00280     or_imm.set_decoder (op=0x02, op3=0x02, is=0x01);
- 00281    
- 00282     orcc_reg.set_asm ("orcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00283     orcc_reg.set_asm ("tst %reg" , rs1="%g0", rs2, rd="%g0"); // synthetic
- 00284     orcc_reg.set_decoder (op=0x02, op3=0x12, is=0x00);
- 00285    
- 00286     orcc_imm.set_asm ("orcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00287     orcc_imm.set_asm ("orcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00288     orcc_imm.set_decoder (op=0x02, op3=0x12, is=0x01);
- 00289    
- 00290     orn_reg.set_asm ("orn %reg, %reg, %reg" , rs1, rs2, rd);
- 00291     orn_reg.set_decoder (op=0x02, op3=0x06, is=0x00);
- 00292    
- 00293     orn_imm.set_asm ("orn %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00294     orn_imm.set_asm ("orn %reg, %imm, %reg" , rs1, simm13, rd);
- 00295     orn_imm.set_decoder (op=0x02, op3=0x06, is=0x01);
- 00296    
- 00297     orncc_reg.set_asm ("orncc %reg, %reg, %reg" , rs1, rs2, rd);
- 00298     orncc_reg.set_decoder (op=0x02, op3=0x16, is=0x00);
- 00299    
- 00300     orncc_imm.set_asm ("orncc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00301     orncc_imm.set_asm ("orncc %reg, %imm, %reg" , rs1, simm13, rd);
- 00302     orncc_imm.set_decoder (op=0x02, op3=0x16, is=0x01);
- 00303    
- 00304     xor_reg.set_asm ("xor %reg, %reg, %reg" , rs1, rs2, rd);
- 00305     xor_reg.set_decoder (op=0x02, op3=0x03, is=0x00);
- 00306    
- 00307     xor_imm.set_asm ("xor %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00308     xor_imm.set_asm ("xor %reg, %imm, %reg" , rs1, simm13, rd);
- 00309     xor_imm.set_decoder (op=0x02, op3=0x03, is=0x01);
- 00310    
- 00311     xorcc_reg.set_asm ("xorcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00312     xorcc_reg.set_decoder (op=0x02, op3=0x13, is=0x00);
- 00313    
- 00314     xorcc_imm.set_asm ("xorcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00315     xorcc_imm.set_asm ("xorcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00316     xorcc_imm.set_decoder (op=0x02, op3=0x13, is=0x01);
- 00317    
- 00318     xnor_reg.set_asm ("xnor %reg, %reg, %reg" , rs1, rs2, rd);
- 00319     xnor_reg.set_asm ("not %reg, %reg" , rs1, rs2="%g0", rd); // synthetic
- 00320     xnor_reg.set_decoder (op=0x02, op3=0x07, is=0x00);
- 00321    
- 00322     xnor_imm.set_asm ("xnor %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00323     xnor_imm.set_asm ("xnor %reg, %imm, %reg" , rs1, simm13, rd);
- 00324     xnor_imm.set_decoder (op=0x02, op3=0x07, is=0x01);
- 00325    
- 00326     xnorcc_reg.set_asm ("xnorcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00327     xnorcc_reg.set_decoder (op=0x02, op3=0x17, is=0x00);
- 00328    
- 00329     xnorcc_imm.set_asm ("xnorcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00330     xnorcc_imm.set_asm ("xnorcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00331     xnorcc_imm.set_decoder (op=0x02, op3=0x17, is=0x01);
- 00332    
- 00333     sll_reg.set_asm ("sll %reg, %reg, %reg" , rs1, rs2, rd);
- 00334     sll_reg.set_decoder (op=0x02, op3=0x25, is=0x00);
- 00335    
- 00336     sll_imm.set_asm ("sll %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00337     sll_imm.set_asm ("sll %reg, %imm, %reg" , rs1, simm13, rd);
- 00338     sll_imm.set_decoder (op=0x02, op3=0x25, is=0x01);
- 00339    
- 00340     srl_reg.set_asm ("srl %reg, %reg, %reg" , rs1, rs2, rd);
- 00341     srl_reg.set_decoder (op=0x02, op3=0x26, is=0x00);
- 00342    
- 00343     srl_imm.set_asm ("srl %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00344     srl_imm.set_asm ("srl %reg, %imm, %reg" , rs1, simm13, rd);
- 00345     srl_imm.set_decoder (op=0x02, op3=0x26, is=0x01);
- 00346    
- 00347     sra_reg.set_asm ("sra %reg, %reg, %reg" , rs1, rs2, rd);
- 00348     sra_reg.set_decoder (op=0x02, op3=0x27, is=0x00);
- 00349    
- 00350     sra_imm.set_asm ("sra %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00351     sra_imm.set_asm ("sra %reg, %imm, %reg" , rs1, simm13, rd);
- 00352     sra_imm.set_decoder (op=0x02, op3=0x27, is=0x01);
- 00353    
- 00354     add_reg.set_asm ("add %reg, %reg, %reg" , rs1, rs2, rd);
- 00355     add_reg.set_decoder (op=0x02, op3=0x00, is=0x00);
- 00356    
- 00357     add_imm.set_asm ("add %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd); // gas
- 00358     add_imm.set_asm ("add %reg, %imm, %reg" , rs1, simm13, rd);
- 00359     add_imm.set_decoder (op=0x02, op3=0x00, is=0x01);
- 00360    
- 00361     addcc_reg.set_asm ("addcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00362     addcc_reg.set_asm ("btst %reg, %reg" , rs1, rs2, rd="%g0"); // synthetic
- 00363     addcc_reg.set_decoder (op=0x02, op3=0x10, is=0x00);
- 00364    
- 00365     addcc_imm.set_asm ("addcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00366     addcc_imm.set_asm ("addcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00367     addcc_imm.set_asm ("btst %reg, %imm" , rs1, simm13, rd="%g0"); // synthetic
- 00368     addcc_imm.set_decoder (op=0x02, op3=0x10, is=0x01);
- 00369    
- 00370     addx_reg.set_asm ("addx %reg, %reg, %reg" , rs1, rs2, rd);
- 00371     addx_reg.set_decoder (op=0x02, op3=0x08, is=0x00);
- 00372    
- 00373     addx_imm.set_asm ("addx %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00374     addx_imm.set_asm ("addx %reg, %imm, %reg" , rs1, simm13, rd);
- 00375     addx_imm.set_decoder (op=0x02, op3=0x08, is=0x01);
- 00376    
- 00377     addxcc_reg.set_asm ("addxcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00378     addxcc_reg.set_decoder (op=0x02, op3=0x18, is=0x00);
- 00379    
- 00380     addxcc_imm.set_asm ("addxcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00381     addxcc_imm.set_asm ("addxcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00382     addxcc_imm.set_decoder (op=0x02, op3=0x18, is=0x01);
- 00383    
- 00384     sub_reg.set_asm ("sub %reg, %reg, %reg" , rs1, rs2, rd);
- 00385     sub_reg.set_asm ("neg %reg, %reg" , rs1="%g0", rs2, rd); // synthetic
- 00386     sub_reg.set_decoder (op=0x02, op3=0x04, is=0x00);
- 00387    
- 00388     sub_imm.set_asm ("sub %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00389     sub_imm.set_asm ("sub %reg, %imm, %reg" , rs1, simm13, rd);
- 00390     sub_imm.set_decoder (op=0x02, op3=0x04, is=0x01);
- 00391    
- 00392     subcc_reg.set_asm ("subcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00393     subcc_reg.set_asm ("cmp %reg, %reg" , rs1, rs2, rd="%g0"); // synthetic
- 00394     subcc_reg.set_decoder (op=0x02, op3=0x14, is=0x00);
- 00395    
- 00396     subcc_imm.set_asm ("subcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00397     subcc_imm.set_asm ("subcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00398     subcc_imm.set_asm ("cmp %reg, %imm" , rs1, simm13, rd="%g0"); // synthetic
- 00399     subcc_imm.set_decoder (op=0x02, op3=0x14, is=0x01);
- 00400    
- 00401     subx_reg.set_asm ("subx %reg, %reg, %reg" , rs1, rs2, rd);
- 00402     subx_reg.set_decoder (op=0x02, op3=0x0C, is=0x00);
- 00403    
- 00404     subx_imm.set_asm ("subx %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00405     subx_imm.set_asm ("subx %reg, %imm, %reg" , rs1, simm13, rd);
- 00406     subx_imm.set_decoder (op=0x02, op3=0x0C, is=0x01);
- 00407    
- 00408     subxcc_reg.set_asm ("subxcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00409     subxcc_reg.set_decoder (op=0x02, op3=0x1C, is=0x00);
- 00410    
- 00411     subxcc_imm.set_asm ("subxcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00412     subxcc_imm.set_asm ("subxcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00413     subxcc_imm.set_decoder (op=0x02, op3=0x1C, is=0x01);
- 00414    
- 00415     umulcc_imm.set_asm ("umulcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00416     umulcc_imm.set_asm ("umulcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00417     umulcc_imm.set_decoder (op=0x02, op3=0x1A, is=0x01);
- 00418    
- 00419     umul_imm.set_asm ("umul %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00420     umul_imm.set_asm ("umul %reg, %imm, %reg" , rs1, simm13, rd);
- 00421     umul_imm.set_decoder (op=0x02, op3=0x0A, is=0x01);
- 00422    
- 00423     umulcc_reg.set_asm ("umulcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00424     umulcc_reg.set_decoder (op=0x02, op3=0x1A, is=0x00);
- 00425    
- 00426     umul_reg.set_asm ("umul %reg, %reg, %reg" , rs1, rs2, rd);
- 00427     umul_reg.set_decoder (op=0x02, op3=0x0A, is=0x00);
- 00428    
- 00429     smul_imm.set_asm ("smul %reg, %imm, %reg" , rs1, simm13, rd);
- 00430     smul_imm.set_decoder (op=0x02, op3=0x0B, is=0x01);
- 00431    
- 00432     smulcc_imm.set_asm ("smulcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00433     smulcc_imm.set_asm ("smulcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00434     smulcc_imm.set_decoder (op=0x02, op3=0x1B, is=0x01);
- 00435    
- 00436     smul_reg.set_asm ("smul %reg, %reg, %reg" , rs1, rs2, rd);
- 00437     smul_reg.set_decoder (op=0x02, op3=0x0B, is=0x00);
- 00438    
- 00439     smulcc_reg.set_asm ("smulcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00440     smulcc_reg.set_decoder (op=0x02, op3=0x1B, is=0x00);
- 00441    
- 00442     mulscc_reg.set_asm ("mulscc %reg, %reg, %reg" , rs1, rs2, rd);
- 00443     mulscc_reg.set_decoder (op=0x02, op3=0x24, is=0x00);
- 00444    
- 00445     mulscc_imm.set_asm ("mulscc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00446     mulscc_imm.set_asm ("mulscc %reg, %imm, %reg" , rs1, simm13, rd);
- 00447     mulscc_imm.set_decoder (op=0x02, op3=0x24, is=0x01);
- 00448    
- 00449     udiv_reg.set_asm ("udiv %reg, %reg, %reg" , rs1, rs2, rd);
- 00450     udiv_reg.set_decoder (op=0x02, op3=0x0E, is=0x00);
- 00451    
- 00452     udivcc_reg.set_asm ("smul %reg, %reg, %reg" , rs1, rs2, rd);
- 00453     udivcc_reg.set_decoder (op=0x02, op3=0x1E, is=0x00);
- 00454    
- 00455     udiv_imm.set_asm ("udiv %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00456     udiv_imm.set_asm ("udiv %reg, %imm, %reg" , rs1, simm13, rd);
- 00457     udiv_imm.set_decoder (op=0x02, op3=0x0E, is=0x01);
- 00458    
- 00459     udivcc_imm.set_asm ("udivcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00460     udivcc_imm.set_asm ("udivcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00461     udivcc_imm.set_decoder (op=0x02, op3=0x1E, is=0x01);
- 00462    
- 00463     sdiv_reg.set_asm ("sdiv %reg, %reg, %reg" , rs1, rs2, rd);
- 00464     sdiv_reg.set_decoder (op=0x02, op3=0x0F, is=0x00);
- 00465    
- 00466     sdivcc_reg.set_asm ("sdivcc %reg, %reg, %reg" , rs1, rs2, rd);
- 00467     sdivcc_reg.set_decoder (op=0x02, op3=0x1F, is=0x00);
- 00468    
- 00469     sdiv_imm.set_asm ("sdiv %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00470     sdiv_imm.set_asm ("sdiv %reg, %imm, %reg" , rs1, simm13, rd);
- 00471     sdiv_imm.set_decoder (op=0x02, op3=0x0F, is=0x01);
- 00472    
- 00473     sdivcc_imm.set_asm ("sdivcc %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00474     sdivcc_imm.set_asm ("sdivcc %reg, %imm, %reg" , rs1, simm13, rd);
- 00475     sdivcc_imm.set_decoder (op=0x02, op3=0x1F, is=0x01);
- 00476    
- 00477     save_reg.set_asm ("save %reg, %reg, %reg" , rs1, rs2, rd);
- 00478     save_reg.set_asm ("save" , rs1="%g0", rs2="%g0", rd="%g0"); // synthetic
- 00479     save_reg.set_decoder (op=0x02, op3=0x3C, is=0x00);
- 00480    
- 00481     save_imm.set_asm ("save %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00482     save_imm.set_asm ("save %reg, %imm, %reg" , rs1, simm13, rd);
- 00483     save_imm.set_decoder (op=0x02, op3=0x3C, is=0x01);
- 00484    
- 00485     restore_reg.set_asm ("restore %reg, %reg, %reg" , rs1, rs2, rd);
- 00486     restore_reg.set_asm ("restore" , rs1="%g0", rs2="%g0", rd="%g0"); // synthetic
- 00487     restore_reg.set_decoder (op=0x02, op3=0x3D, is=0x00);
- 00488    
- 00489     restore_imm.set_asm ("restore %reg, \%lo(%exp(low)), %reg" , rs1, simm13, rd);
- 00490     restore_imm.set_asm ("restore %reg, %imm, %reg" , rs1, simm13, rd);
- 00491     restore_imm.set_decoder (op=0x02, op3=0x3D, is=0x01);
- 00492    
- 00493     ba.set_asm ("b %exp(pcrel)" , disp22, an=0);
- 00494     ba.set_asm ("ba %exp(pcrel)" , disp22, an=0);
- 00495     ba.set_asm ("ba,a %exp(pcrel)" , disp22, an=1);
- 00496     ba.set_decoder(op=0x00, cond =0x08, op2=0x02);
- 00497    
- 00498     bn.set_asm ("bn %exp(pcrel)" , disp22, an=0);
- 00499     bn.set_asm ("bn,a %exp(pcrel)" , disp22, an=1);
- 00500     bn.set_decoder(op=0x00, cond =0x00, op2=0x02);
- 00501    
- 00502     bne.set_asm ("bne%[anul] %exp(pcrel)" , an, disp22);
- 00503     bne.set_asm ("bnz%[anul] %exp(pcrel)" , an, disp22);
- 00504     bne.set_decoder(op=0x00, cond =0x09, op2=0x02);
- 00505    
- 00506     be.set_asm ("be%[anul] %exp(pcrel)" , an, disp22);
- 00507     be.set_asm ("bz%[anul] %exp(pcrel)" , an, disp22);
- 00508     be.set_decoder(op=0x00, cond =0x01, op2=0x02);
- 00509    
- 00510     bg.set_asm ("bg%[anul] %exp(pcrel)" , an, disp22);
- 00511     bg.set_decoder(op=0x00, cond =0x0A, op2=0x02);
- 00512    
- 00513     ble.set_asm ("ble%[anul] %exp(pcrel)" , an, disp22);
- 00514     ble.set_decoder(op=0x00, cond =0x02, op2=0x02);
- 00515    
- 00516     bge.set_asm ("bge%[anul] %exp(pcrel)" , an, disp22);
- 00517     bge.set_decoder(op=0x00, cond =0x0B, op2=0x02);
- 00518    
- 00519     bl.set_asm ("bl%[anul] %exp(pcrel)" , an, disp22);
- 00520     bl.set_decoder(op=0x00, cond =0x03, op2=0x02);
- 00521    
- 00522     bgu.set_asm ("bgu%[anul] %exp(pcrel)" , an, disp22);
- 00523     bgu.set_decoder(op=0x00, cond =0x0C, op2=0x02);
- 00524    
- 00525     bleu.set_asm ("bleu%[anul] %exp(pcrel)" , an, disp22);
- 00526     bleu.set_decoder(op=0x00, cond =0x04, op2=0x02);
- 00527    
- 00528     bcc.set_asm ("bcc%anul %exp(pcrel)" , an, disp22);
- 00529     bcc.set_asm ("bgeu%[anul] %exp(pcrel)" , an, disp22);
- 00530     bcc.set_decoder(op=0x00, cond =0x0D, op2=0x02);
- 00531    
- 00532     bcs.set_asm ("bcs%[anul] %exp(pcrel)" , an, disp22);
- 00533     bcs.set_asm ("blu%[anul] %exp(pcrel)" , an, disp22);
- 00534     bcs.set_decoder(op=0x00, cond =0x05, op2=0x02);
- 00535    
- 00536     bpos.set_asm ("bpos%[anul] %exp(pcrel)" , an, disp22);
- 00537     bpos.set_decoder(op=0x00, cond =0x0E, op2=0x02);
- 00538    
- 00539     bneg.set_asm ("bneg%[anul] %exp(pcrel)" , an, disp22);
- 00540     bneg.set_decoder(op=0x00, cond =0x06, op2=0x02);
- 00541    
- 00542     bvc.set_asm ("bvc%[anul] %exp(pcrel)" , an, disp22);
- 00543     bvc.set_decoder(op=0x00, cond =0x0F, op2=0x02);
- 00544    
- 00545     bvs.set_asm ("bvs%[anul] %exp(pcrel)" , an, disp22);
- 00546     bvs.set_decoder(op=0x00, cond =0x07, op2=0x02);
- 00547    
- 00548     call.set_asm ("call %exp(pcrel)" , disp30);
- 00549     call.set_decoder (op=0x01);
- 00550    
- 00551     rdy.set_asm ("rd \%y, %reg" , rs1=0, rd);
- 00552     rdy.set_asm ("mov \%y, %reg" , rs1=0, rd);
- 00553     rdy.set_decoder (op=0x02, op3=0x28);
- 00554    
- 00555     jmpl_reg.set_asm ("jmp %reg" , rs1, rs2=0, rd=0); // gas
- 00556     jmpl_reg.set_asm ("call %reg" , rs1, rs2=0, rd=15); // gas
- 00557     jmpl_reg.set_asm ("jmpl %reg + %reg, %reg" , rs1, rs2, rd);
- 00558     jmpl_reg.set_asm ("jmp %reg + %reg" , rs1, rs2, rd="%g0"); // synthetic
- 00559     jmpl_reg.set_asm ("call %reg + %reg" , rs1, rs2, rd="%o7"); // synthetic
- 00560     jmpl_reg.set_decoder (op=0x02, op3=0x38, is=0x00);
- 00561    
- 00562     jmpl_imm.set_asm ("jmpl %reg + %imm, %reg" , rs1, simm13, rd);
- 00563     jmpl_imm.set_asm ("jmpl %imm + %reg, %reg" , simm13, rs1, rd);
- 00564     jmpl_imm.set_asm ("jmp %reg + %imm" , rs1, simm13, rd="%g0"); // synthetic
- 00565     jmpl_imm.set_asm ("call %reg + %imm" , rs1, simm13, rd="%o7"); // synthetic
- 00566     jmpl_imm.set_asm ("ret" , rs1="%i7", simm13=8, rd="%g0"); // synthetic
- 00567     jmpl_imm.set_asm ("retl" , rs1="%o7", simm13=8, rd="%g0"); // synthetic
- 00568     jmpl_imm.set_decoder (op=0x02, op3=0x38, is=0x01);
- 00569    
- 00570     wry_reg.set_asm ("wr %reg, \%y" , rs1, rd=0, rs2=0);
- 00571     wry_reg.set_asm ("wr %reg, %reg, \%y" , rs1, rs2, rd=0);
- 00572     wry_reg.set_asm ("mov %reg, \%y" , rs1="%g0", rs2, rd=0);
- 00573     wry_reg.set_decoder (op=0x02, op3=0x30, is=0x00);
- 00574    
- 00575     wry_imm.set_asm ("wr %reg, %imm, \%y" , rs1, simm13, rd=0);
- 00576     wry_imm.set_asm ("mov %imm, \%y" , simm13, rs1="%g0", rd=0);
- 00577     wry_imm.set_decoder (op=0x02, op3=0x30, is=0x01);
- 00578    
- 00579     trap_imm.set_asm("t%cond %imm" , cond , imm7, r1=0);
- 00580     trap_imm.set_decoder (op=0x02, is=1, op2a=0x3A);
- 00581    
- 00582     trap_reg.set_asm("t%cond %reg" , cond , rs2);
- 00583     trap_reg.set_decoder (op=0x02, is=0, op2a=0x3A);
- 00584    
- 00585     unimplemented.set_asm ("unimp %imm" , imm22);
- 00586     unimplemented.set_decoder (op=0x00,rd=0x00,op2=0x00);
- 00587    
- 00588     pseudo_instr ("not %reg" ) {
- 00589     "xnor %0, \%g0, %0" ;
- 00590     }
- 00591    
- 00592     pseudo_instr ("neg %reg" ) {
- 00593     "sub \%g0, %0, %0" ;
- 00594     }
- 00595    
- 00596     pseudo_instr ("inc %reg" ) {
- 00597     "add %0, 1, %0" ;
- 00598     }
- 00599    
- 00600     pseudo_instr ("inc %imm, %reg" ) {
- 00601     "add %1, %0, %1" ;
- 00602     }
- 00603    
- 00604     pseudo_instr ("inccc %reg" ) {
- 00605     "addcc %0, 1, %0" ;
- 00606     }
- 00607    
- 00608     pseudo_instr ("inccc %imm, %reg" ) {
- 00609     "addcc %1, %0, %1" ;
- 00610     }
- 00611    
- 00612     pseudo_instr ("dec %reg" ) {
- 00613     "sub %0, 1, %0" ;
- 00614     }
- 00615    
- 00616     pseudo_instr ("dec %imm, %reg" ) {
- 00617     "sub %1, %0, %1" ;
- 00618     }
- 00619    
- 00620     pseudo_instr ("deccc %reg" ) {
- 00621     "subcc %0, 1, %0" ;
- 00622     }
- 00623    
- 00624     pseudo_instr ("deccc %imm, %reg" ) {
- 00625     "subcc %0, %1, %0" ;
- 00626     }
- 00627    
- 00628     pseudo_instr ("set %addr, %reg" ) {
- 00629     "sethi \%hi(%0), %1" ;
- 00630     "or %1, \%lo(%0), %1" ;
- 00631     }
- 00632    
- 00633     pseudo_instr ("set %imm, %reg" ) { // only valid when -4096 <= imm <= 4095
- 00634     "or \%g0, %0, %1" ;
- 00635     }
- 00636    
- 00637     pseudo_instr ("bset %reg, %reg" ) {
- 00638     "or %1, %0, %1" ;
- 00639     }
- 00640    
- 00641     pseudo_instr ("bset %imm, %reg" ) {
- 00642     "or %1, %0, %1" ;
- 00643     }
- 00644    
- 00645     pseudo_instr ("bclr %reg, %reg" ) {
- 00646     "andn %1, %0, %1" ;
- 00647     }
- 00648    
- 00649     pseudo_instr ("bclr %imm, %reg" ) {
- 00650     "andn %1, %0, %1" ;
- 00651     }
- 00652    
- 00653     pseudo_instr ("btog %reg, %reg" ) {
- 00654     "xor %1, %0, %1" ;
- 00655     }
- 00656    
- 00657     pseudo_instr ("btog %imm, %reg" ) {
- 00658     "xor %1, %0, %1" ;
- 00659     }
- 00660    
- 00661     pseudo_instr ("call %exp, %imm" ) {
- 00662     "call %0" ;
- 00663     }
- 00664    
- 00665     pseudo_instr ("call %reg, %imm" ) {
- 00666     "call %0" ;
- 00667     }
- 00668    
- 00669    
- 00670     /********************************************************/
- 00671     /* Optional properties to optimize compiled simulation */
- 00672     /********************************************************/
- 00673    
- 00674     call.is_jump (ac_pc+(disp30<<2));
- 00675     call.delay (1);
- 00676     call.behavior (writeReg(15, ac_pc););
- 00677    
- 00678     jmpl_reg.is_jump (readReg(rs1) + readReg(rs2) - ac_start_addr);
- 00679     jmpl_reg.delay (1);
- 00680     jmpl_reg.behavior (writeReg(rd, ac_pc););
- 00681    
- 00682     jmpl_imm.is_jump (readReg(rs1) + simm13);
- 00683     jmpl_imm.delay (1);
- 00684     jmpl_imm.behavior (writeReg(rd, ac_pc););
- 00685    
- 00686    
- 00687    
- 00688     ba.is_branch (ac_pc+(disp22<<2));
- 00689     ba.cond (1);
- 00690     ba.delay (1);
- 00691     ba.delay_cond (!an);
- 00692    
- 00693     bn.is_branch (ac_pc+(disp22<<2));
- 00694     bn.cond (0);
- 00695     bn.delay (1);
- 00696     bn.delay_cond (!an);
- 00697    
- 00698     bne.is_branch (ac_pc+(disp22<<2));
- 00699     bne.cond (!PSR_icc_z);
- 00700     bne.delay (1);
- 00701     bne.delay_cond (!PSR_icc_z || !an);
- 00702    
- 00703     be.is_branch (ac_pc+(disp22<<2));
- 00704     be.cond (PSR_icc_z);
- 00705     be.delay (1);
- 00706     be.delay_cond (PSR_icc_z || !an);
- 00707    
- 00708     bg.is_branch (ac_pc+(disp22<<2));
- 00709     bg.cond (!(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v)));
- 00710     bg.delay (1);
- 00711     bg.delay_cond (!(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v)) || !an);
- 00712    
- 00713     ble.is_branch (ac_pc+(disp22<<2));
- 00714     ble.cond (PSR_icc_z ||(PSR_icc_n ^PSR_icc_v));
- 00715     ble.delay (1);
- 00716     ble.delay_cond (PSR_icc_z ||(PSR_icc_n ^PSR_icc_v) || !an);
- 00717    
- 00718     bge.is_branch (ac_pc+(disp22<<2));
- 00719     bge.cond (!(PSR_icc_n ^PSR_icc_v));
- 00720     bge.delay (1);
- 00721     bge.delay_cond (!(PSR_icc_n ^PSR_icc_v) || !an);
- 00722    
- 00723     bl.is_branch (ac_pc+(disp22<<2));
- 00724     bl.cond (PSR_icc_n ^PSR_icc_v);
- 00725     bl.delay (1);
- 00726     bl.delay_cond (PSR_icc_n ^PSR_icc_v || !an);
- 00727    
- 00728     bgu.is_branch (ac_pc+(disp22<<2));
- 00729     bgu.cond (!(PSR_icc_c ||PSR_icc_z));
- 00730     bgu.delay (1);
- 00731     bgu.delay_cond (!(PSR_icc_c ||PSR_icc_z) || !an);
- 00732    
- 00733     bleu.is_branch (ac_pc+(disp22<<2));
- 00734     bleu.cond (PSR_icc_c ||PSR_icc_z);
- 00735     bleu.delay (1);
- 00736     bleu.delay_cond (PSR_icc_c ||PSR_icc_z || !an);
- 00737    
- 00738     bcc.is_branch (ac_pc+(disp22<<2));
- 00739     bcc.cond (!PSR_icc_c);
- 00740     bcc.delay (1);
- 00741     bcc.delay_cond (!PSR_icc_c || !an);
- 00742    
- 00743     bcs.is_branch (ac_pc+(disp22<<2));
- 00744     bcs.cond (PSR_icc_c);
- 00745     bcs.delay (1);
- 00746     bcs.delay_cond (PSR_icc_c || !an);
- 00747    
- 00748     bpos.is_branch (ac_pc+(disp22<<2));
- 00749     bpos.cond (!PSR_icc_n);
- 00750     bpos.delay (1);
- 00751     bpos.delay_cond (!PSR_icc_n || !an);
- 00752    
- 00753     bneg.is_branch (ac_pc+(disp22<<2));
- 00754     bneg.cond (PSR_icc_n);
- 00755     bneg.delay (1);
- 00756     bneg.delay_cond (PSR_icc_n || !an);
- 00757    
- 00758     bvc.is_branch (ac_pc+(disp22<<2));
- 00759     bvc.cond (!PSR_icc_v);
- 00760     bvc.delay (1);
- 00761     bvc.delay_cond (!PSR_icc_v || !an);
- 00762    
- 00763     bvs.is_branch (ac_pc+(disp22<<2));
- 00764     bvs.cond (PSR_icc_v);
- 00765     bvs.delay (1);
- 00766     bvs.delay_cond (PSR_icc_v || !an);
- 00767    
- 00768     };
- 00769     };
- 00770    
- 00771    
- 00772