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powerpc Architechture Description
powerpc Other Properties
ISA (ac_isa):
Name: powerpc_isa.ac
M1 (ac_format):
Format Description: opcd 6; rs 5; ra 5; rb 5; mb 5; me 5; rc 1;
Instructions: rlwnm_ rlwnm
M2 (ac_format):
Format Description: opcd 6; rs 5; ra 5; sh 5; mb 5; me 5; rc 1;
Instructions: rlwinm rlwimi rlwinm_ rlwimi_
X25 (ac_format):
Format Description: opcd 6; 0 5; 0 5; e 1; 0 4; xog 10; 0 1;
X24 (ac_format):
Format Description: opcd 6; 0 5; 0 5; 0 5; xog 10; 0 1;
X21 (ac_format):
Format Description: opcd 6; to 5; ra 5; rb 5; xog 10; 0 1;
X20 (ac_format):
Format Description: opcd 6; bf 3; 0 2; 0 5; 0 5; xog 10; 0 1;
X23 (ac_format):
Format Description: opcd 6; 0 5; ra 5; rb 5; xog 10; 0 1;
X22 (ac_format):
Format Description: opcd 6; bt 5; 0 5; 0 5; xog 10; rc 1;
XFX2 (ac_format):
Format Description: opcd 6; rt 5; dcrf 10; xog 10; 0 1;
XFX3 (ac_format):
Format Description: opcd 6; rs 5; 0 1; xfm 8; 0 1; xog 10; 0 1;
Instructions: mtcrf
XFX1 (ac_format):
Format Description: opcd 6; rt 5; sprf 10; xog 10; 0 1;
Instructions: mfspr
XO2 (ac_format):
Format Description: opcd 6; rt 5; ra 5; rb 5; 0 1; xos 9; rc 1;
Instructions: mulhwu mulhw mulhwu_ mulhw_
XO3 (ac_format):
Format Description: opcd 6; rt 5; ra 5; 0 5; oe 1; xos 9; rc 1;
Instructions: subfzeo nego neg_ subfze subfze_ addzeo_ addmeo_ addze neg addze_ subfzeo_ nego_ addme_ subfme_ addmeo addzeo subfme addme subfmeo_ subfmeo
XFX4 (ac_format):
Format Description: opcd 6; rs 5; sprf 10; xog 10; 0 1;
Instructions: mtspr
XFX5 (ac_format):
Format Description: opcd 6; rs 5; dcrf 10; xog 10; 0 1;
I1 (ac_format):
Format Description: opcd 6; li 24 s; aa 1; lk 1;
Instructions: bl bla ba b
X14 (ac_format):
Format Description: opcd 6; rs 5; 0 5; rb 5; xog 10; 0 1;
X8 (ac_format):
Format Description: opcd 6; rs 5; ra 5; rb 5; xog 10; 1 1;
X9 (ac_format):
Format Description: opcd 6; rs 5; ra 5; rb 5; xog 10; 0 1;
Instructions: stwx stswx sthbrx sthx stbx sthux stwbrx stbux stwux
X2 (ac_format):
Format Description: opcd 6; rt 5; ra 5; rb 5; xog 10; 0 1;
Instructions: lhaux lwzx lwzux lbzux lhzux lhax lwbrx lswx lbzx lhzx lhbrx
X3 (ac_format):
Format Description: opcd 6; rt 5; ra 5; nb 5; xog 10; 0 1;
Instructions: lswi
X1 (ac_format):
Format Description: opcd 6; rt 5; ra 5; rb 5; xog 10; rc 1;
Instructions: mullhwu_ mullhwu mullhw_ mullhw
X6 (ac_format):
Format Description: opcd 6; rt 5; 0 5; 0 5; xog 10; 0 1;
Instructions: mfcr
X7 (ac_format):
Format Description: opcd 6; rs 5; ra 5; rb 5; xog 10; rc 1;
Instructions: sraw_ srw_ orc_ nor_ nor nand_ slw_ xxor_ nand sraw ore orc ande_ eqv_ ore_ srw ande andc eqv slw andc_ xxor
X4 (ac_format):
Format Description: opcd 6; rt 5; ra 5; ws 5; xog 10; 0 1;
X5 (ac_format):
Format Description: opcd 6; rt 5; 0 5; rb 5; xog 10; 0 1;
X18 (ac_format):
Format Description: opcd 6; bf 3; 0 2; 0 5; 0 5; xog 10; 0 1;
Instructions: mcrxr
X19 (ac_format):
Format Description: opcd 6; bf 3; 0 2; 0 5; u 5; xog 10; rc 1;
X10 (ac_format):
Format Description: opcd 6; rs 5; ra 5; nb 5; xog 10; 0 1;
Instructions: stswi
X11 (ac_format):
Format Description: opcd 6; rs 5; ra 5; ws 5; xog 10; 0 1;
X12 (ac_format):
Format Description: opcd 6; rs 5; ra 5; sh 5; xog 10; rc 1;
Instructions: srawi srawi_
X13 (ac_format):
Format Description: opcd 6; rs 5; ra 5; 0 5; xog 10; rc 1;
Instructions: cntlzw extsb_ extsb extsh cntlzw_ extsh_
SC1 (ac_format):
Format Description: opcd 6; 0 5; 0 5; 0 4; lev 7; 0 3; 1 1; 0 1;
Instructions: sc
X15 (ac_format):
Format Description: opcd 6; rs 5; 0 5; 0 5; xog 10; 0 1;
X16 (ac_format):
Format Description: opcd 6; bf 3; 0 1; l 1; ra 5; rb 5; xog 10; 0 1;
Instructions: cmpl cmp
X17 (ac_format):
Format Description: opcd 6; bf 3; 0 2; bfa 3; 0 2; 0 5; xog 10; rc 1;
XL4 (ac_format):
Format Description: opcd 6; 0 5; 0 5; 0 5; xog 10; 0 1;
XL3 (ac_format):
Format Description: opcd 6; bf 3; 0 2; bfa 3; 0 2; 0 5; xog 10; 0 1;
Instructions: mcrf
XO1 (ac_format):
XL2 (ac_format):
Format Description: opcd 6; bo 5; bi 5; 0 3; bh 2; xog 10; lk 1;
Instructions: bcctr bclrl bclr bcctrl
B1 (ac_format):
Format Description: opcd 6; bo 5; bi 5; bd 14 s; aa 1; lk 1;
Instructions: bcla bc bcl bca
D6 (ac_format):
Format Description: opcd 6; bf 3; 0 1; l 1; ra 5; ui 16;
Instructions: cmpli
D7 (ac_format):
Format Description: opcd 6; to 5; ra 5; si 16 s;
D4 (ac_format):
Format Description: opcd 6; rs 5; ra 5; ui 16;
Instructions: ori xoris oris andi_ andis_ xori
D5 (ac_format):
Format Description: opcd 6; bf 3; 0 1; l 1; ra 5; si 16 s;
Instructions: cmpi
D2 (ac_format):
Format Description: opcd 6; rs 5; ra 5; si 16 s;
D3 (ac_format):
Format Description: opcd 6; rs 5; ra 5; d 16 s;
Instructions: stwu sthu stmw stbu stb sth stw
XL1 (ac_format):
Format Description: opcd 6; bt 5; ba 5; bb 5; xog 10; 0 1;
Instructions: crnor crxor crnand cror crand creqv crorc crandc
D1 (ac_format):
Format Description: opcd 6; rt 5; ra 5; d 16 s;
Instructions: lwzu subfic lhau mulli addi addic lmw addis lbzu lhzu lwz lbz lha lhz addic_
rlwnm_ (ac_instr):
Instruction Type: M1
Decoder: opcd=23; rc=1;
ASM: rlwnm. %imm, %imm, %imm, %imm, %imm
ASM: ra
ASM: rs
ASM: rb
ASM: mb
ASM: me
crnor (ac_instr):
Instruction Type: XL1
Decoder: opcd=19; xog=33;
ASM: crnor %reg, %reg, %reg
ASM: bt
ASM: ba
ASM: bb
subfco (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=8; rc=0;
ASM: subfco %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
mullw_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=235; rc=1;
ASM: mullw. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
bcla (ac_instr):
Instruction Type: B1
Decoder: opcd=16; aa=1; lk=1;
ASM: bcla %imm, %exp, %addr(pcrel)
ASM: bo
ASM: bi
ASM: bd
Is Branch: bd<<2
Condition: test_Branch_Cond(bo,bi)
Behavior: LR.write(ac_pc+4);
subfzeo (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=1; xos=200; rc=0;
ASM: subfzeo %reg, %reg
ASM: rt
ASM: ra
mullhwu_ (ac_instr):
Instruction Type: X1
Decoder: opcd=4; xog=392; rc=1;
ASM: mullhwu. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
divwou_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; xos=459; oe=1; rc=1;
ASM: divwou. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
nego (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; xos=104; oe=1; rc=0;
ASM: nego %reg, %reg
ASM: rt
ASM: ra
cmpi (ac_instr):
Instruction Type: D5
Decoder: opcd=11; l=0;
ASM: ['cmpwi %imm, %reg, %imm', 'bf', 'ra', 'si', 'l', '0']
ASM: ['cmpi %reg, %imm, %reg, %imm', 'bf', 'l', 'ra', 'si']
cmpl (ac_instr):
Instruction Type: X16
Decoder: opcd=31; l=0; xog=32;
ASM: ['cmplw %reg, %reg, %reg', 'bf', 'ra', 'rb', 'l', '0']
ASM: ['cmpl %imm, %imm, %reg, %reg', 'bf', 'l', 'ra', 'rb']
subfc (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=8; rc=0;
ASM: subfc %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
sraw_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=792; rc=1;
ASM: sraw. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
stwu (ac_instr):
Instruction Type: D3
Decoder: opcd=37;
ASM: ['stwu %reg, %imm (%reg)', 'rs', 'd', 'ra']
ASM: ['stwu %reg, %imm (%reg)', 'rs', 'd', 'ra']
cmpli (ac_instr):
Instruction Type: D6
Decoder: opcd=10; l=0;
ASM: ['cmplwi %reg, %reg, %imm', 'bf', 'ra', 'ui', 'l', '0']
ASM: ['cmpli %reg, %imm, %reg, %imm', 'bf', 'l', 'ra', 'ui']
neg_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; xos=104; oe=0; rc=1;
ASM: neg. %reg, %reg
ASM: rt
ASM: ra
srawi (ac_instr):
Instruction Type: X12
Decoder: opcd=31; xog=824; rc=0;
ASM: srawi %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: sh
stwx (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=151;
ASM: stwx %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
stswi (ac_instr):
Instruction Type: X10
Decoder: opcd=31; xog=725;
ASM: stswi %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: nb
subfze (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=0; xos=200; rc=0;
ASM: subfze %reg, %reg
ASM: rt
ASM: ra
add (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=266; rc=0;
ASM: add %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lhaux (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=375;
ASM: lhaux %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
cntlzw (ac_instr):
Instruction Type: X13
Decoder: opcd=31; xog=26; rc=0;
ASM: cntlzw %reg, %reg
ASM: ra
ASM: rs
rlwnm (ac_instr):
Instruction Type: M1
Decoder: opcd=23; rc=0;
ASM: rlwnm %imm, %imm, %imm, %imm, %imm
ASM: ra
ASM: rs
ASM: rb
ASM: mb
ASM: me
srw_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=536; rc=1;
ASM: srw. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
mullwo (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=235; rc=0;
ASM: mullwo %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
stswx (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=661;
ASM: stswx %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
subfze_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=0; xos=200; rc=1;
ASM: subfze. %reg, %reg
ASM: rt
ASM: ra
orc_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=412; rc=1;
ASM: orc. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
addc (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=10; rc=0;
ASM: addc %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
sthbrx (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=918;
ASM: sthbrx %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
addzeo_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=1; xos=202; rc=1;
ASM: addzeo. %reg, %reg
ASM: rt
ASM: ra
nor_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=124; rc=1;
ASM: nor. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
addc_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=10; rc=1;
ASM: addc. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
crxor (ac_instr):
Instruction Type: XL1
Decoder: opcd=19; xog=193;
ASM: crxor %reg, %reg, %reg
ASM: bt
ASM: ba
ASM: bb
addmeo_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=1; xos=234; rc=1;
ASM: addmeo. %reg, %reg
ASM: rt
ASM: ra
mcrxr (ac_instr):
Instruction Type: X18
Decoder: opcd=31; xog=512;
ASM: mcrxr %imm
ASM: bf
mullw (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=235; rc=0;
ASM: mullw %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lwzx (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=23;
ASM: lwzx %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
subfo (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=40; rc=0;
ASM: subfo %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lwzu (ac_instr):
Instruction Type: D1
Decoder: opcd=33;
ASM: ['lwzu %reg, %imm (%reg)', 'rt', 'd', 'ra']
ASM: ['lwzu %reg, %exp@l(%reg)', 'rt', 'd', 'ra']
subfic (ac_instr):
Instruction Type: D1
Decoder: opcd=8;
ASM: subfic %reg, %reg, %exp
ASM: rt
ASM: ra
ASM: d
addze (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=0; xos=202; rc=0;
ASM: addze %reg, %reg
ASM: rt
ASM: ra
subfe (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=136; rc=0;
ASM: subfe %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
nor (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=124; rc=0;
ASM: nor %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
nand_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=476; rc=1;
ASM: nand. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
slw_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=24; rc=1;
ASM: slw. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
subf_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=40; rc=1;
ASM: subf. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
bcctr (ac_instr):
Instruction Type: XL2
Decoder: opcd=19; xog=528; lk=0;
ASM: ['bctr', 'bo', 20, 'bi', '0', 'bh', '0']
ASM: ['bcctr %reg, %reg, %reg', 'bo', 'bi', 'bh']
Is Branch: CTR.read() & 0xFFFFFFFC
Condition: test_Branch_Cond(bo,bi)
lwzux (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=55;
ASM: lwzux %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
sthx (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=407;
ASM: sthx %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
rlwinm (ac_instr):
Instruction Type: M2
Decoder: opcd=21; rc=0;
ASM: rlwinm %reg, %reg, %exp, %imm, %exp
ASM: ra
ASM: rs
ASM: sh
ASM: mb
ASM: me
mfcr (ac_instr):
Instruction Type: X6
Decoder: opcd=31; xog=19;
ASM: mfcr %imm
ASM: rt
lbzux (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=119;
ASM: lbzux %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
sthu (ac_instr):
Instruction Type: D3
Decoder: opcd=45;
ASM: ['sthu %reg, %imm (%reg)', 'rs', 'd', 'ra']
ASM: ['sthu %reg, %exp@l(%reg)', 'rs', 'd', 'ra']
cmp (ac_instr):
Instruction Type: X16
Decoder: opcd=31; l=0; xog=0;
ASM: ['cmpw %imm, %imm, %imm', 'bf', 'ra', 'rb', 'l', '0']
ASM: ['cmp %imm, %imm, %reg, %reg', 'bf', 'l', 'ra', 'rb']
subfc_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=8; rc=1;
ASM: subfc. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
add_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=266; rc=1;
ASM: add. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
crnand (ac_instr):
Instruction Type: XL1
Decoder: opcd=19; xog=225;
ASM: crnand %reg, %reg, %reg
ASM: bt
ASM: ba
ASM: bb
rlwimi (ac_instr):
Instruction Type: M2
Decoder: opcd=20; rc=0;
ASM: rlwimi %reg, %reg, %exp, %imm, %exp
ASM: ra
ASM: rs
ASM: sh
ASM: mb
ASM: me
lhzux (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=311;
ASM: lhzux %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lhax (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=343;
ASM: lhax %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
xxor_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=316; rc=1;
ASM: xor. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
lhau (ac_instr):
Instruction Type: D1
Decoder: opcd=43;
ASM: ['lhau %reg, %imm (%reg)', 'rt', 'd', 'ra']
ASM: ['lhau %reg, %exp@l(%reg)', 'rt', 'd', 'ra']
neg (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; xos=104; oe=0; rc=0;
ASM: neg %reg, %reg
ASM: rt
ASM: ra
mulli (ac_instr):
Instruction Type: D1
Decoder: opcd=7;
ASM: mulli %reg, %reg, %exp
ASM: rt
ASM: ra
ASM: d
rlwinm_ (ac_instr):
Instruction Type: M2
Decoder: opcd=21; rc=1;
ASM: rlwinm. %reg, %reg, %exp, %imm, %exp
ASM: ra
ASM: rs
ASM: sh
ASM: mb
ASM: me
nand (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=476; rc=0;
ASM: nand %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
bl (ac_instr):
Instruction Type: I1
Decoder: opcd=18; aa=0; lk=1;
ASM: bl %addr(pcrel)
ASM: li
Is Jump: ac_pc+(li<<2)
Behavior: LR.write(ac_pc+4);
adde (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=138; rc=0;
ASM: adde %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lwbrx (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=534;
ASM: lwbrx %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
adde_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=138; rc=1;
ASM: adde. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
mfspr (ac_instr):
Instruction Type: XFX1
Decoder: opcd=31; xog=339;
ASM: [['mfctr %imm', 'rt', 'sprf', 288], ['mflr %imm', 'rt', 'sprf', 256]]
ASM: ['mfspr %imm, %imm', 'rt', 'sprf']
addo (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=266; rc=0;
ASM: addo %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
divwu_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; xos=459; oe=0; rc=1;
ASM: divwu. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
extsb_ (ac_instr):
Instruction Type: X13
Decoder: opcd=31; xog=954; rc=1;
ASM: extsb. %reg, %reg
ASM: ra
ASM: rs
bla (ac_instr):
Instruction Type: I1
Decoder: opcd=18; aa=1; lk=1;
ASM: bla %addr(pcrel)
ASM: li
Is Jump: li<<2
Behavior: LR.write(ac_pc+4);
addi (ac_instr):
Instruction Type: D1
Decoder: opcd=14;
ASM: [[['li %reg, %exp', 'rt', 'ra', '0', 'd'], ['li %reg, %exp(carry)@ha', 'rt', 'ra', '0', 'd']], ['la %reg, %exp@l(%imm)', 'rt', 'd', 'ra']]
ASM: ['addi %reg, %reg, %exp', 'rt', 'ra', 'd']
addze_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=0; xos=202; rc=1;
ASM: addze. %reg, %reg
ASM: rt
ASM: ra
ba (ac_instr):
Instruction Type: I1
Decoder: opcd=18; aa=1; lk=0;
ASM: ba %addr(pcrel)
ASM: li
Is Jump: li<<2
bc (ac_instr):
Instruction Type: B1
Decoder: opcd=16; aa=0; lk=0;
ASM: bc %imm, %exp, %addr(pcrel)
ASM: bo
ASM: bi
ASM: bd
Is Branch: ac_pc+(bd<<2)
Condition: test_Branch_Cond(bo,bi)
addic (ac_instr):
Instruction Type: D1
Decoder: opcd=12;
ASM: addic %reg, %reg, %exp
ASM: rt
ASM: ra
ASM: d
subfzeo_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=1; xos=200; rc=1;
ASM: subfzeo. %reg, %reg
ASM: rt
ASM: ra
lswx (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=533;
ASM: lswx %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
stmw (ac_instr):
Instruction Type: D3
Decoder: opcd=47;
ASM: ['stmw %reg, %imm (%reg)', 'rs', 'd', 'ra']
ASM: ['stmw %reg, %exp@l(%reg)', 'rs', 'd', 'ra']
divw_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; xos=491; oe=0; rc=1;
ASM: divw. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lmw (ac_instr):
Instruction Type: D1
Decoder: opcd=46;
ASM: ['lmw %reg, %imm (%reg)', 'rt', 'd', 'ra']
ASM: ['lmw %reg, %exp@l(%reg)', 'rt', 'd', 'ra']
sraw (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=792; rc=0;
ASM: sraw %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
subfco_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=8; rc=1;
ASM: subfco. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
ori (ac_instr):
Instruction Type: D4
Decoder: opcd=24;
ASM: ori %reg, %reg, %imm
ASM: ra
ASM: rs
ASM: ui
addis (ac_instr):
Instruction Type: D1
Decoder: opcd=15;
ASM: [['lis %reg, %exp', 'rt', 'ra', '0', 'd'], ['lis %reg, %exp(carry)@ha', 'rt', 'ra', '0', 'd']]
ASM: ['addis %reg, %reg, %exp', 'rt', 'ra', 'd']
ore (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=444; rc=0;
ASM: or %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
orc (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=412; rc=0;
ASM: orc %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
ande_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=28; rc=1;
ASM: and. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
eqv_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=284; rc=1;
ASM: eqv. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
mulhwu (ac_instr):
Instruction Type: XO2
Decoder: opcd=31; xos=11; rc=0;
ASM: mulhwu %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
xoris (ac_instr):
Instruction Type: D4
Decoder: opcd=27;
ASM: xoris %reg, %reg, %imm
ASM: ra
ASM: rs
ASM: ui
lbzx (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=87;
ASM: lbzx %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lbzu (ac_instr):
Instruction Type: D1
Decoder: opcd=35;
ASM: ['lbzu %reg, %imm (%reg)', 'rt', 'd', 'ra']
ASM: ['lbzu %reg, %exp@l(%reg)', 'rt', 'd', 'ra']
ore_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=444; rc=1;
ASM: or. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
srw (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=536; rc=0;
ASM: srw %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
nego_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; xos=104; oe=1; rc=1;
ASM: nego. %reg, %reg
ASM: rt
ASM: ra
addeo_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=138; rc=1;
ASM: addeo. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
addme_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=0; xos=234; rc=1;
ASM: addme. %reg, %reg
ASM: rt
ASM: ra
lhzx (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=279;
ASM: lhzx %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lhzu (ac_instr):
Instruction Type: D1
Decoder: opcd=41;
ASM: ['lhzu %reg, %imm (%reg)', 'rt', 'd', 'ra']
ASM: ['lhzu %reg, %exp@l(%reg)', 'rt', 'd', 'ra']
subf (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=40; rc=0;
ASM: subf %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
divw (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; xos=491; oe=0; rc=0;
ASM: divw %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
subfe_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=0; xos=136; rc=1;
ASM: subfe. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
stbx (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=215;
ASM: stbx %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
sthux (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=439;
ASM: sthux %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
subfme_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=0; xos=232; rc=1;
ASM: subfme. %reg, %reg
ASM: rt
ASM: ra
stbu (ac_instr):
Instruction Type: D3
Decoder: opcd=39;
ASM: ['stbu %reg, %imm (%reg)', 'rs', 'd', 'ra']
ASM: ['stbu %reg, %exp@l(%reg)', 'rs', 'd', 'ra']
lwz (ac_instr):
Instruction Type: D1
Decoder: opcd=32;
ASM: ['lwz %imm, %imm (%imm)', 'rt', 'd', 'ra']
ASM: ['lwz %imm, %exp@l(%imm)', 'rt', 'd', 'ra']
subfeo (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=136; rc=0;
ASM: subfeo %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lswi (ac_instr):
Instruction Type: X3
Decoder: opcd=31; xog=597;
ASM: lswi %imm, %imm, %imm
ASM: rt
ASM: ra
ASM: nb
ande (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=28; rc=0;
ASM: and %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
andc (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=60; rc=0;
ASM: andc %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
eqv (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=284; rc=0;
ASM: eqv %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
divwo (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; xos=491; oe=1; rc=0;
ASM: divwo %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
addmeo (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=1; xos=234; rc=0;
ASM: addmeo %reg, %reg
ASM: rt
ASM: ra
addzeo (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=1; xos=202; rc=0;
ASM: addzeo %reg, %reg
ASM: rt
ASM: ra
oris (ac_instr):
Instruction Type: D4
Decoder: opcd=25;
ASM: oris %reg, %reg, %imm
ASM: ra
ASM: rs
ASM: ui
subfeo_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=136; rc=1;
ASM: subfeo. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
andi_ (ac_instr):
Instruction Type: D4
Decoder: opcd=28;
ASM: andi. %reg, %reg, %imm
ASM: ra
ASM: rs
ASM: ui
mtcrf (ac_instr):
Instruction Type: XFX3
Decoder: opcd=31; xog=144;
ASM: mtcrf %imm, %imm
ASM: xfm
ASM: rs
subfo_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=40; rc=1;
ASM: subfo. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
mullhwu (ac_instr):
Instruction Type: X1
Decoder: opcd=4; xog=392; rc=0;
ASM: mullhwu %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
extsb (ac_instr):
Instruction Type: X13
Decoder: opcd=31; xog=954; rc=0;
ASM: extsb %reg, %reg
ASM: ra
ASM: rs
cror (ac_instr):
Instruction Type: XL1
Decoder: opcd=19; xog=449;
ASM: cror %reg, %reg, %reg
ASM: bt
ASM: ba
ASM: bb
extsh (ac_instr):
Instruction Type: X13
Decoder: opcd=31; xog=922; rc=0;
ASM: extsh %reg, %reg
ASM: ra
ASM: rs
cntlzw_ (ac_instr):
Instruction Type: X13
Decoder: opcd=31; xog=26; rc=1;
ASM: cntlzw. %reg, %reg
ASM: ra
ASM: rs
subfme (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=0; xos=232; rc=0;
ASM: subfme %reg, %reg
ASM: rt
ASM: ra
stwbrx (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=662;
ASM: stwbrx %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
divwu (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; xos=459; oe=0; rc=0;
ASM: divwu %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
crand (ac_instr):
Instruction Type: XL1
Decoder: opcd=19; xog=257;
ASM: crand %reg, %reg, %reg
ASM: bt
ASM: ba
ASM: bb
b (ac_instr):
Instruction Type: I1
Decoder: opcd=18; aa=0; lk=0;
ASM: b %addr(pcrel)
ASM: li
Is Jump: ac_pc+(li<<2)
addco_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=10; rc=1;
ASM: addco. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
stb (ac_instr):
Instruction Type: D3
Decoder: opcd=38;
ASM: ['stb %reg, %imm (%reg)', 'rs', 'd', 'ra']
ASM: ['stb %reg, %exp@l(%reg)', 'rs', 'd', 'ra']
slw (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=24; rc=0;
ASM: slw %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
sth (ac_instr):
Instruction Type: D3
Decoder: opcd=44;
ASM: ['sth %reg, %imm (%reg)', 'rs', 'd', 'ra']
ASM: ['sth %reg, %exp@l(%reg)', 'rs', 'd', 'ra']
addo_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=266; rc=1;
ASM: addo. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
mullhw_ (ac_instr):
Instruction Type: X1
Decoder: opcd=4; xog=424; rc=1;
ASM: mullhw. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
stw (ac_instr):
Instruction Type: D3
Decoder: opcd=36;
ASM: ['stw %reg, %imm (%reg)', 'rs', 'd', 'ra']
ASM: ['stw %reg, %exp@l(%reg)', 'rs', 'd', 'ra']
bclrl (ac_instr):
Instruction Type: XL2
Decoder: opcd=19; xog=16; lk=1;
ASM: bclrl %reg, %reg, %reg
ASM: bo
ASM: bi
ASM: bh
Is Branch: LR.read() & 0xFFFFFFFC
Condition: test_Branch_Cond(bo,bi)
Behavior: LR.write(ac_pc+4);
extsh_ (ac_instr):
Instruction Type: X13
Decoder: opcd=31; xog=922; rc=1;
ASM: extsh. %reg, %reg
ASM: ra
ASM: rs
addco (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=10; rc=0;
ASM: addco %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lbz (ac_instr):
Instruction Type: D1
Decoder: opcd=34;
ASM: ['lbz %reg, %imm (%reg)', 'rt', 'd', 'ra']
ASM: ['lbz %reg, %exp@l(%reg)', 'rt', 'd', 'ra']
bclr (ac_instr):
Instruction Type: XL2
Decoder: opcd=19; xog=16; lk=0;
ASM: ['blr', 'bo', 20, 'bi', '0', 'bh', '0']
ASM: ['bclr %reg, %reg, %reg', 'bo', 'bi', 'bh']
Is Branch: LR.read() & 0xFFFFFFFC
Condition: test_Branch_Cond(bo,bi)
mtspr (ac_instr):
Instruction Type: XFX4
Decoder: opcd=31; xog=467;
ASM: [['mtctr %imm', 'rs', 'sprf', 288], ['mtlr %imm', 'rs', 'sprf', 256]]
ASM: ['mtspr %imm, %imm', 'sprf', 'rs']
andis_ (ac_instr):
Instruction Type: D4
Decoder: opcd=29;
ASM: andis. %reg, %reg, %imm
ASM: ra
ASM: rs
ASM: ui
andc_ (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=60; rc=1;
ASM: andc. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
xxor (ac_instr):
Instruction Type: X7
Decoder: opcd=31; xog=316; rc=0;
ASM: xor %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: rb
stbux (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=247;
ASM: stbux %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
creqv (ac_instr):
Instruction Type: XL1
Decoder: opcd=19; xog=289;
ASM: creqv %reg, %reg, %reg
ASM: bt
ASM: ba
ASM: bb
lhbrx (ac_instr):
Instruction Type: X2
Decoder: opcd=31; xog=790;
ASM: lhbrx %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
rlwimi_ (ac_instr):
Instruction Type: M2
Decoder: opcd=20; rc=1;
ASM: rlwimi. %reg, %reg, %exp, %imm, %exp
ASM: ra
ASM: rs
ASM: sh
ASM: mb
ASM: me
mulhw (ac_instr):
Instruction Type: XO2
Decoder: opcd=31; xos=75; rc=0;
ASM: mulhw %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
divwou (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; xos=459; oe=1; rc=0;
ASM: divwou %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
addeo (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=138; rc=0;
ASM: addeo %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
bcctrl (ac_instr):
Instruction Type: XL2
Decoder: opcd=19; xog=528; lk=1;
ASM: ['bctrl', 'bo', 20, 'bi', '0', 'bh', '0']
ASM: ['bcctrl %reg, %reg, %reg', 'bo', 'bi', 'bh']
Is Branch: CTR.read() & 0xFFFFFFFC
Condition: test_Branch_Cond(bo,bi)
Behavior: LR.write(ac_pc+4);
mcrf (ac_instr):
Instruction Type: XL3
Decoder: opcd=19; xog=0;
ASM: mcrf %imm, %imm
ASM: bf
ASM: bfa
stwux (ac_instr):
Instruction Type: X9
Decoder: opcd=31; xog=183;
ASM: stwux %reg, %reg, %reg
ASM: rs
ASM: ra
ASM: rb
mulhwu_ (ac_instr):
Instruction Type: XO2
Decoder: opcd=31; xos=11; rc=1;
ASM: mulhwu. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
xori (ac_instr):
Instruction Type: D4
Decoder: opcd=26;
ASM: xori %reg, %reg, %imm
ASM: ra
ASM: rs
ASM: ui
addme (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=0; xos=234; rc=0;
ASM: addme %reg, %reg
ASM: rt
ASM: ra
srawi_ (ac_instr):
Instruction Type: X12
Decoder: opcd=31; xog=824; rc=1;
ASM: srawi. %reg, %reg, %reg
ASM: ra
ASM: rs
ASM: sh
bcl (ac_instr):
Instruction Type: B1
Decoder: opcd=16; aa=0; lk=1;
ASM: bcl %imm, %exp, %addr(pcrel)
ASM: bo
ASM: bi
ASM: bd
Is Branch: ac_pc+(bd<<2)
Condition: test_Branch_Cond(bo,bi)
Behavior: LR.write(ac_pc+4);
subfmeo_ (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=1; xos=232; rc=1;
ASM: subfmeo. %reg, %reg
ASM: rt
ASM: ra
lha (ac_instr):
Instruction Type: D1
Decoder: opcd=42;
ASM: ['lha %reg, %imm (%reg)', 'rt', 'd', 'ra']
ASM: ['lha %reg, %exp@l(%reg)', 'rt', 'd', 'ra']
mulhw_ (ac_instr):
Instruction Type: XO2
Decoder: opcd=31; xos=75; rc=1;
ASM: mulhw. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
divwo_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; xos=491; oe=1; rc=1;
ASM: divwo. %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
subfmeo (ac_instr):
Instruction Type: XO3
Decoder: opcd=31; oe=1; xos=232; rc=0;
ASM: subfmeo %reg, %reg
ASM: rt
ASM: ra
mullwo_ (ac_instr):
Instruction Type: XO1
Decoder: opcd=31; oe=1; xos=235; rc=1;
ASM: mullw %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
bca (ac_instr):
Instruction Type: B1
Decoder: opcd=16; aa=1; lk=0;
ASM: bca %imm, %exp, %addr(pcrel)
ASM: bo
ASM: bi
ASM: bd
Is Branch: bd<<2
Condition: test_Branch_Cond(bo,bi)
crorc (ac_instr):
Instruction Type: XL1
Decoder: opcd=19; xog=417;
ASM: crorc %reg, %reg, %reg
ASM: bt
ASM: ba
ASM: bb
sc (ac_instr):
Instruction Type: SC1
Decoder: opcd=17;
ASM: sc %imm
ASM: lev
mullhw (ac_instr):
Instruction Type: X1
Decoder: opcd=4; xog=424; rc=0;
ASM: mullhw %reg, %reg, %reg
ASM: rt
ASM: ra
ASM: rb
lhz (ac_instr):
Instruction Type: D1
Decoder: opcd=40;
ASM: ['lhz %reg, %imm (%reg)', 'rt', 'd', 'ra']
ASM: ['lhz %reg, %exp@l(%reg)', 'rt', 'd', 'ra']
addic_ (ac_instr):
Instruction Type: D1
Decoder: opcd=13;
ASM: addic. %reg, %reg, %exp
ASM: rt
ASM: ra
ASM: d
crandc (ac_instr):
Instruction Type: XL1
Decoder: opcd=19; xog=129;
ASM: crandc %reg, %reg, %reg
ASM: bt
ASM: ba
ASM: bb