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sparcv8 Architechture Description
sparcv8 Other Properties
ISA (ac_isa):
Name: sparcv8_isa.ac
Type_F3B (ac_format):
Type_F3A (ac_format):
Type_F2A (ac_format):
Format Description: op 2; rd 5; op2 3; imm22 22;
Instructions: nop unimplemented sethi
Type_FT (ac_format):
Format Description: op 2; r1 1; cond 4; op2a 6; rs1 5; is 1; (('r2a', '8'), ('rs2', '5')) (('r2b', '6'), ('imm7', '7'));
Instructions: trap_reg trap_imm
Type_F2B (ac_format):
Format Description: op 2; an 1; cond 4; op2 3; disp22 22 s;
Instructions: bvs bvc bne bleu ble bn be bg ba bl bge bpos bgu bneg bcc bcs
Type_F1 (ac_format):
Format Description: op 2; disp30 30;
Instructions: call
bvs (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=7; op2=2;
ASM: bvs%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: PSR_icc_v
Delay Condition: PSR_icc_v || !an
srl_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=38; is=0;
ASM: srl %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
umul_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=10; is=0;
ASM: umul %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
andncc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=21; is=0;
ASM: andncc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
ldsb_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=9; is=1;
ASM: [[['ldsb [%reg + \\%lo(%exp(low))], %reg', 'rs1', 'simm13', 'rd'], ['ldsb [%reg + %imm], %reg', 'rs1', 'simm13', 'rd']], ['ldsb [%imm + %reg], %reg', 'simm13', 'rs1', 'rd']]
ASM: ['ldsb [%imm], %reg', 'simm13', 'rd', 'rs1', '%g0']
orncc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=22; is=0;
ASM: orncc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
bvc (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=15; op2=2;
ASM: bvc%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: !PSR_icc_v
Delay Condition: !PSR_icc_v || !an
andn_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=5; is=1;
ASM: ['andn %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['andn %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
std_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=7; is=0;
ASM: ['std %reg, [%reg + %reg]', 'rd', 'rs1', 'rs2']
ASM: ['std %reg, [%reg]', 'rd', 'rs1', 'rs2', '%g0']
lduh_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=2; is=1;
ASM: [[['lduh [%reg + \\%lo(%exp(low))], %reg', 'rs1', 'simm13', 'rd'], ['lduh [%reg + %imm], %reg', 'rs1', 'simm13', 'rd']], ['lduh [%imm + %reg], %reg', 'simm13', 'rs1', 'rd']]
ASM: ['lduh [%imm], %reg', 'simm13', 'rd', 'rs1', '%g0']
xnorcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=23; is=0;
ASM: xnorcc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
sll_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=37; is=0;
ASM: sll %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
addcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=16; is=1;
ASM: [['addcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd'], ['addcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']]
ASM: ['btst %reg, %imm', 'rs1', 'simm13', 'rd', '%g0']
restore_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=61; is=1;
ASM: ['restore %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['restore %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
stb_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=5; is=1;
ASM: [[[[[['stb %reg, [%reg + \\%lo(%exp(low))]', 'rd', 'rs1', 'simm13'], ['stb %reg, [%reg + %imm]', 'rd', 'rs1', 'simm13']], ['stb %reg, [%imm + %reg]', 'rd', 'simm13', 'rs1']], ['stb %reg, [%imm]', 'rd', 'simm13', 'rs1', '%g0']], ['clrb [%reg + %imm]', 'rd', '%g0', 'rs1', 'simm13']], ['clrb [%imm + %reg]', 'rd', '%g0', 'simm13', 'rs1']]
ASM: ['clrb [%imm]', 'rd', '%g0', 'rs1', '%g0', 'simm13']
sth_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=6; is=1;
ASM: [[[[[['sth %reg, [%reg + \\%lo(%exp(low))]', 'rd', 'rs1', 'simm13'], ['sth %reg, [%reg + %imm]', 'rd', 'rs1', 'simm13']], ['sth %reg, [%imm + %reg]', 'rd', 'simm13', 'rs1']], ['sth %reg, [%imm]', 'rd', 'simm13', 'rs1', '%g0']], ['clrh [%reg + %imm]', 'rd', '%g0', 'rs1', 'simm13']], ['clrh [%imm + %reg]', 'rd', '%g0', 'simm13', 'rs1']]
ASM: ['clrh [%imm]', 'rd', '%g0', 'rs1', '%g0', 'simm13']
jmpl_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=56; is=0;
ASM: [[[['jmp %reg', 'rs1', 'rs2', '0', 'rd', '0'], ['call %reg', 'rs1', 'rs2', '0', 'rd', '15']], ['jmpl %reg + %reg, %reg', 'rs1', 'rs2', 'rd']], ['jmp %reg + %reg', 'rs1', 'rs2', 'rd', '%g0']]
ASM: ['call %reg + %reg', 'rs1', 'rs2', 'rd', '%o7']
Is Jump: readReg(rs1) + readReg(rs2) - ac_start_addr
Delay: 1
Behavior: writeReg(rd, ac_pc);
bne (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=9; op2=2;
ASM: ['bne%[anul] %exp(pcrel)', 'an', 'disp22']
ASM: ['bnz%[anul] %exp(pcrel)', 'an', 'disp22']
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: !PSR_icc_z
Delay Condition: !PSR_icc_z || !an
sdiv_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=15; is=0;
ASM: sdiv %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
sub_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=4; is=0;
ASM: ['sub %reg, %reg, %reg', 'rs1', 'rs2', 'rd']
ASM: ['neg %reg, %reg', 'rs1', '%g0', 'rs2', 'rd']
sra_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=39; is=0;
ASM: sra %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
ld_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=0; is=1;
ASM: [[['ld [%reg + \\%lo(%exp(low))], %reg', 'rs1', 'simm13', 'rd'], ['ld [%reg + %imm], %reg', 'rs1', 'simm13', 'rd']], ['ld [%imm + %reg], %reg', 'simm13', 'rs1', 'rd']]
ASM: ['ld [%imm], %reg', 'simm13', 'rd', 'rs1', '%g0']
nop (ac_instr):
Instruction Type: Type_F2A
Decoder: op=0; rd=0; op2=4; imm22=0;
ASM: nop
andcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=17; is=1;
ASM: [['andcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd'], ['andcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']]
ASM: ['btst %imm, %reg', 'simm13', 'rs1', 'rd', '%g0']
restore_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=61; is=0;
ASM: ['restore %reg, %reg, %reg', 'rs1', 'rs2', 'rd']
ASM: ['restore', 'rs1', '%g0', 'rs2', '%g0', 'rd', '%g0']
subcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=20; is=0;
ASM: ['subcc %reg, %reg, %reg', 'rs1', 'rs2', 'rd']
ASM: ['cmp %reg, %reg', 'rs1', 'rs2', 'rd', '%g0']
or_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=2; is=0;
ASM: [['or %reg, %reg, %reg', 'rs1', 'rs2', 'rd'], ['clr %reg', 'rs1', '%g0', 'rs2', '%g0', 'rd']]
ASM: ['mov %reg, %reg', 'rs1', '%g0', 'rs2', 'rd']
orcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=18; is=1;
ASM: ['orcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['orcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
udiv_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=14; is=0;
ASM: udiv %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
bleu (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=4; op2=2;
ASM: bleu%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: PSR_icc_c ||PSR_icc_z
Delay Condition: PSR_icc_c ||PSR_icc_z || !an
st_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=4; is=1;
ASM: [[[[[['st %reg, [%reg + \\%lo(%exp(low))]', 'rd', 'rs1', 'simm13'], ['st %reg, [%reg + %imm]', 'rd', 'rs1', 'simm13']], ['st %reg, [%imm + %reg]', 'rd', 'simm13', 'rs1']], ['st %reg, [%imm]', 'rd', 'simm13', 'rs1', '%g0']], ['clr [%reg + %imm]', 'rd', '%g0', 'rs1', 'simm13']], ['clr [%imm + %reg]', 'rd', '%g0', 'simm13', 'rs1']]
ASM: ['clr [%imm]', 'rd', '%g0', 'rs1', '%g0', 'simm13']
subx_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=12; is=0;
ASM: subx %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
wry_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=48; is=0;
ASM: [['wr %reg, \\%y', 'rs1', 'rd', '0', 'rs2', '0'], ['wr %reg, %reg, \\%y', 'rs1', 'rs2', 'rd', '0']]
ASM: ['mov %reg, \\%y', 'rs1', '%g0', 'rs2', 'rd', '0']
add_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=0; is=0;
ASM: add %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
swap_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=15; is=0;
ASM: ['swap [%reg + %reg], %reg', 'rs1', 'rs2', 'rd']
ASM: ['swap [%reg], %reg', 'rs1', 'rd', 'rs2', '%g0']
lduh_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=2; is=0;
ASM: ['lduh [%reg + %reg], %reg', 'rs1', 'rs2', 'rd']
ASM: ['lduh [%reg], %reg', 'rs1', 'rd', 'rs2', '%g0']
ldstub_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=13; is=1;
ASM: [[['ldstub [%reg + \\%lo(%exp(low))], %reg', 'rs1', 'simm13', 'rd'], ['ldstub [%reg + %imm], %reg', 'rs1', 'simm13', 'rd']], ['ldstub [%imm + %reg], %reg', 'simm13', 'rs1', 'rd']]
ASM: ['ldstub [%imm], %reg', 'simm13', 'rd', 'rs1', '%g0']
xor_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=3; is=0;
ASM: xor %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
save_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=60; is=0;
ASM: ['save %reg, %reg, %reg', 'rs1', 'rs2', 'rd']
ASM: ['save', 'rs1', '%g0', 'rs2', '%g0', 'rd', '%g0']
mulscc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=36; is=1;
ASM: ['mulscc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['mulscc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
sdiv_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=15; is=1;
ASM: ['sdiv %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['sdiv %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
ldd_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=3; is=0;
ASM: ['ldd [%reg + %reg], %reg', 'rs1', 'rs2', 'rd']
ASM: ['ldd [%reg], %reg', 'rs1', 'rd', 'rs2', '%g0']
umulcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=26; is=0;
ASM: umulcc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
sdivcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=31; is=0;
ASM: sdivcc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
ble (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=2; op2=2;
ASM: ble%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: PSR_icc_z ||(PSR_icc_n ^PSR_icc_v)
Delay Condition: PSR_icc_z ||(PSR_icc_n ^PSR_icc_v) || !an
sub_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=4; is=1;
ASM: ['sub %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['sub %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
bn (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=0; op2=2;
ASM: ['bn %exp(pcrel)', 'disp22', 'an', '0']
ASM: ['bn,a %exp(pcrel)', 'disp22', 'an', '1']
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: 0
Delay Condition: !an
be (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=1; op2=2;
ASM: ['be%[anul] %exp(pcrel)', 'an', 'disp22']
ASM: ['bz%[anul] %exp(pcrel)', 'an', 'disp22']
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: PSR_icc_z
Delay Condition: PSR_icc_z || !an
bg (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=10; op2=2;
ASM: bg%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: !(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v))
Delay Condition: !(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v)) || !an
ba (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=8; op2=2;
ASM: [['b %exp(pcrel)', 'disp22', 'an', '0'], ['ba %exp(pcrel)', 'disp22', 'an', '0']]
ASM: ['ba,a %exp(pcrel)', 'disp22', 'an', '1']
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: 1
Delay Condition: !an
bl (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=3; op2=2;
ASM: bl%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: PSR_icc_n ^PSR_icc_v
Delay Condition: PSR_icc_n ^PSR_icc_v || !an
xorcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=19; is=1;
ASM: ['xorcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['xorcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
orn_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=6; is=0;
ASM: orn %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
xnor_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=7; is=1;
ASM: ['xnor %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['xnor %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
trap_reg (ac_instr):
Instruction Type: Type_FT
Decoder: op=2; is=0; op2a=58;
ASM: t%cond %reg
ASM: cond
ASM: rs2
bge (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=11; op2=2;
ASM: bge%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: !(PSR_icc_n ^PSR_icc_v)
Delay Condition: !(PSR_icc_n ^PSR_icc_v) || !an
rdy (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=40;
ASM: ['rd \\%y, %reg', 'rs1', '0', 'rd']
ASM: ['mov \\%y, %reg', 'rs1', '0', 'rd']
bpos (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=14; op2=2;
ASM: bpos%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: !PSR_icc_n
Delay Condition: !PSR_icc_n || !an
subxcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=28; is=0;
ASM: subxcc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
bgu (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=12; op2=2;
ASM: bgu%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: !(PSR_icc_c ||PSR_icc_z)
Delay Condition: !(PSR_icc_c ||PSR_icc_z) || !an
addx_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=8; is=0;
ASM: addx %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
ld_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=0; is=0;
ASM: ['ld [%reg + %reg], %reg', 'rs1', 'rs2', 'rd']
ASM: ['ld [%reg], %reg', 'rs1', 'rd', 'rs2', '%g0']
udivcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=30; is=0;
ASM: smul %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
ldub_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=1; is=0;
ASM: ['ldub [%reg + %reg], %reg', 'rs1', 'rs2', 'rd']
ASM: ['ldub [%reg], %reg', 'rs1', 'rd', 'rs2', '%g0']
and_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=1; is=0;
ASM: and %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
st_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=4; is=0;
ASM: [[['st %reg, [%reg + %reg]', 'rd', 'rs1', 'rs2'], ['st %reg, [%reg]', 'rd', 'rs1', 'rs2', '%g0']], ['clr [%reg + %reg]', 'rd', '%g0', 'rs1', 'rs2']]
ASM: ['clr [%reg]', 'rd', '%g0', 'rs1', 'rs2', '%g0']
udivcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=30; is=1;
ASM: ['udivcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['udivcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
udiv_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=14; is=1;
ASM: ['udiv %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['udiv %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
sra_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=39; is=1;
ASM: ['sra %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['sra %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
sth_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=6; is=0;
ASM: [[['sth %reg, [%reg + %reg]', 'rd', 'rs1', 'rs2'], ['sth %reg, [%reg]', 'rd', 'rs1', 'rs2', '%g0']], ['clrh [%reg + %reg]', 'rd', '%g0', 'rs1', 'rs2']]
ASM: ['clrh [%reg]', 'rd', '%g0', 'rs1', 'rs2', '%g0']
xnorcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=23; is=1;
ASM: ['xnorcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['xnorcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
addcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=16; is=0;
ASM: ['addcc %reg, %reg, %reg', 'rs1', 'rs2', 'rd']
ASM: ['btst %reg, %reg', 'rs1', 'rs2', 'rd', '%g0']
ldsb_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=9; is=0;
ASM: ['ldsb [%reg + %reg], %reg', 'rs1', 'rs2', 'rd']
ASM: ['ldsb [%reg], %reg', 'rs1', 'rd', 'rs2', '%g0']
subx_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=12; is=1;
ASM: ['subx %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['subx %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
or_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=2; is=1;
ASM: [['or %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd'], ['or %reg, %imm, %reg', 'rs1', 'simm13', 'rd']]
ASM: ['mov %imm, %reg', 'rs1', '%g0', 'simm13', 'rd']
andn_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=5; is=0;
ASM: andn %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
call (ac_instr):
Instruction Type: Type_F1
Decoder: op=1;
ASM: call %exp(pcrel)
ASM: disp30
Is Jump: ac_pc+(disp30<<2)
Delay: 1
Behavior: writeReg(15, ac_pc);
ldsh_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=10; is=0;
ASM: ['ldsh [%reg + %reg], %reg', 'rs1', 'rs2', 'rd']
ASM: ['ldsh [%reg], %reg', 'rs1', 'rd', 'rs2', '%g0']
sll_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=37; is=1;
ASM: ['sll %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['sll %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
addxcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=24; is=0;
ASM: addxcc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
andncc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=21; is=1;
ASM: ['andncc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['andncc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
umul_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=10; is=1;
ASM: ['umul %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['umul %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
unimplemented (ac_instr):
Instruction Type: Type_F2A
Decoder: op=0; rd=0; op2=0;
ASM: unimp %imm
ASM: imm22
ldsh_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=10; is=1;
ASM: [[['ldsh [%reg + \\%lo(%exp(low))], %reg', 'rs1', 'simm13', 'rd'], ['ldsh [%reg + %imm], %reg', 'rs1', 'simm13', 'rd']], ['ldsh [%imm + %reg], %reg', 'simm13', 'rs1', 'rd']]
ASM: ['ldsh [%imm], %reg', 'simm13', 'rd', 'rs1', '%g0']
save_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=60; is=1;
ASM: ['save %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['save %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
subcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=20; is=1;
ASM: [['subcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd'], ['subcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']]
ASM: ['cmp %reg, %imm', 'rs1', 'simm13', 'rd', '%g0']
smul_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=11; is=1;
ASM: smul %reg, %imm, %reg
ASM: rs1
ASM: simm13
ASM: rd
and_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=1; is=1;
ASM: ['and %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['and %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
andcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=17; is=0;
ASM: ['andcc %reg, %reg, %reg', 'rs1', 'rs2', 'rd']
ASM: ['btst %reg, %reg', 'rs2', 'rs1', 'rd', '%g0']
xnor_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=7; is=0;
ASM: ['xnor %reg, %reg, %reg', 'rs1', 'rs2', 'rd']
ASM: ['not %reg, %reg', 'rs1', 'rs2', '%g0', 'rd']
xorcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=19; is=0;
ASM: xorcc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
std_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=7; is=1;
ASM: [[['std %reg, [%reg + \\%lo(%exp(low))]', 'rd', 'rs1', 'simm13'], ['std %reg, [%reg + %imm]', 'rd', 'rs1', 'simm13']], ['std %reg, [%imm + %reg]', 'rd', 'simm13', 'rs1']]
ASM: ['std %reg, [%imm]', 'rd', 'simm13', 'rs1', '%g0']
xor_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=3; is=1;
ASM: ['xor %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['xor %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
bneg (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=6; op2=2;
ASM: bneg%[anul] %exp(pcrel)
ASM: an
ASM: disp22
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: PSR_icc_n
Delay Condition: PSR_icc_n || !an
addxcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=24; is=1;
ASM: ['addxcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['addxcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
umulcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=26; is=1;
ASM: ['umulcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['umulcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
subxcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=28; is=1;
ASM: ['subxcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['subxcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
sdivcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=31; is=1;
ASM: ['sdivcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['sdivcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
add_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=0; is=1;
ASM: ['add %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['add %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
smulcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=27; is=0;
ASM: smulcc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
swap_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=15; is=1;
ASM: [[['swap [%reg + \\%lo(%exp(low))], %reg', 'rs1', 'simm13', 'rd'], ['swap [%reg + %imm], %reg', 'rs1', 'simm13', 'rd']], ['swap [%imm + %reg], %reg', 'simm13', 'rs1', 'rd']]
ASM: ['swap [%imm], %reg', 'simm13', 'rd', 'rs1', '%g0']
srl_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=38; is=1;
ASM: ['srl %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['srl %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
jmpl_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=56; is=1;
ASM: [[[[['jmpl %reg + %imm, %reg', 'rs1', 'simm13', 'rd'], ['jmpl %imm + %reg, %reg', 'simm13', 'rs1', 'rd']], ['jmp %reg + %imm', 'rs1', 'simm13', 'rd', '%g0']], ['call %reg + %imm', 'rs1', 'simm13', 'rd', '%o7']], ['ret', 'rs1', '%i7', 'simm13', '8', 'rd', '%g0']]
ASM: ['retl', 'rs1', '%o7', 'simm13', '8', 'rd', '%g0']
Is Jump: readReg(rs1) + simm13
Delay: 1
Behavior: writeReg(rd, ac_pc);
orncc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=22; is=1;
ASM: ['orncc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['orncc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
sethi (ac_instr):
Instruction Type: Type_F2A
Decoder: op=0; op2=4;
ASM: ['sethi %exp, %reg', 'imm22', 'rd']
ASM: ['sethi \\%hi(%exp(high)), %reg', 'imm22', 'rd']
wry_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=48; is=1;
ASM: ['wr %reg, %imm, \\%y', 'rs1', 'simm13', 'rd', '0']
ASM: ['mov %imm, \\%y', 'simm13', 'rs1', '%g0', 'rd', '0']
smulcc_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=27; is=1;
ASM: ['smulcc %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['smulcc %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
smul_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=11; is=0;
ASM: smul %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
orn_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=6; is=1;
ASM: ['orn %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['orn %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
ldub_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=1; is=1;
ASM: [[['ldub [%reg + \\%lo(%exp(low))], %reg', 'rs1', 'simm13', 'rd'], ['ldub [%reg + %imm], %reg', 'rs1', 'simm13', 'rd']], ['ldub [%imm + %reg], %reg', 'simm13', 'rs1', 'rd']]
ASM: ['ldub [%imm], %reg', 'simm13', 'rd', 'rs1', '%g0']
orcc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=18; is=0;
ASM: ['orcc %reg, %reg, %reg', 'rs1', 'rs2', 'rd']
ASM: ['tst %reg', 'rs1', '%g0', 'rs2', 'rd', '%g0']
mulscc_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=2; op3=36; is=0;
ASM: mulscc %reg, %reg, %reg
ASM: rs1
ASM: rs2
ASM: rd
stb_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=5; is=0;
ASM: [[['stb %reg, [%reg + %reg]', 'rd', 'rs1', 'rs2'], ['stb %reg, [%reg]', 'rd', 'rs1', 'rs2', '%g0']], ['clrb [%reg + %reg]', 'rd', '%g0', 'rs1', 'rs2']]
ASM: ['clrb [%reg]', 'rd', '%g0', 'rs1', 'rs2', '%g0']
bcc (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=13; op2=2;
ASM: ['bcc%anul %exp(pcrel)', 'an', 'disp22']
ASM: ['bgeu%[anul] %exp(pcrel)', 'an', 'disp22']
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: !PSR_icc_c
Delay Condition: !PSR_icc_c || !an
ldstub_reg (ac_instr):
Instruction Type: Type_F3A
Decoder: op=3; op3=13; is=0;
ASM: ['ldstub [%reg + %reg], %reg', 'rs1', 'rs2', 'rd']
ASM: ['ldstub [%reg], %reg', 'rs1', 'rd', 'rs2', '%g0']
addx_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=2; op3=8; is=1;
ASM: ['addx %reg, \\%lo(%exp(low)), %reg', 'rs1', 'simm13', 'rd']
ASM: ['addx %reg, %imm, %reg', 'rs1', 'simm13', 'rd']
trap_imm (ac_instr):
Instruction Type: Type_FT
Decoder: op=2; is=1; op2a=58;
ASM: t%cond %imm
ASM: cond
ASM: imm7
ASM: r1
ASM: 0
ldd_imm (ac_instr):
Instruction Type: Type_F3B
Decoder: op=3; op3=3; is=1;
ASM: [[['ldd [%reg + \\%lo(%exp(low))], %reg', 'rs1', 'simm13', 'rd'], ['ldd [%reg + %imm], %reg', 'rs1', 'simm13', 'rd']], ['ldd [%imm + %reg], %reg', 'simm13', 'rs1', 'rd']]
ASM: ['ldd [%imm], %reg', 'simm13', 'rd', 'rs1', '%g0']
bcs (ac_instr):
Instruction Type: Type_F2B
Decoder: op=0; cond=5; op2=2;
ASM: ['bcs%[anul] %exp(pcrel)', 'an', 'disp22']
ASM: ['blu%[anul] %exp(pcrel)', 'an', 'disp22']
Is Branch: ac_pc+(disp22<<2)
Delay: 1
Condition: PSR_icc_c
Delay Condition: PSR_icc_c || !an