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- 00001     /**
- 00002     \file mips1_isa.ac
- 00003     \author Sandro Rigo
- 00004     Marcus Bartholomeu
- 00005     Alexandro Baldassin (acasm information)
- 00006    
- 00007     The ArchC Team
- 00008     http://www.archc.org/
- 00009    
- 00010     Computer Systems Laboratory (LSC)
- 00011     IC-UNICAMP
- 00012     http://www.lsc.ic.unicamp.br/
- 00013    
- 00014     \version 1.0
- 00015     \date Thu, 29 Jun 2006 14:49:08 -0300
- 00016    
- 00017     \brief The ArchC MIPS-I functional model.
- 00018    
- 00019     \note Copyright (C) 2002-2006 --- The ArchC Team
- 00020    
- 00021     \details
- 00022     This program is free software; you can redistribute it and/or modify
- 00023     it under the terms of the GNU General Public License as published by
- 00024     the Free Software Foundation; either version 2 of the License, or
- 00025     (at your option) any later version.
- 00026    
- 00027     This program is distributed in the hope that it will be useful,
- 00028     but WITHOUT ANY WARRANTY; without even the implied warranty of
- 00029     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- 00030     GNU General Public License for more details.
- 00031    
- 00032     You should have received a copy of the GNU General Public License
- 00033     along with this program; if not, write to the Free Software
- 00034     Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- 00035     \end
- 00036     */
- 00037    
- 00038     AC_ISA (mips1){
- 00039    
- 00040     ac_format Type_R = "%op:6 %rs:5 %rt:5 %rd:5 %shamt:5 %func:6" ;
- 00041     ac_format Type_I = "%op:6 %rs:5 %rt:5 %imm:16:s" ;
- 00042     ac_format Type_J = "%op:6 %addr:26" ;
- 00043    
- 00044     ac_instr lb, lbu, lh, lhu, lw, lwl, lwr;
- 00045     ac_instr sb, sh, sw, swl, swr;
- 00046     ac_instr addi, addiu, slti, sltiu, andi, ori, xori, lui;
- 00047     ac_instr add, addu, sub, subu, slt, sltu;
- 00048     ac_instr instr_and, instr_or, instr_xor, instr_nor;
- 00049     ac_instr nop, sll, srl, sra, sllv, srlv, srav;
- 00050     ac_instr mult, multu, div, divu;
- 00051     ac_instr mfhi, mthi, mflo, mtlo;
- 00052     ac_instr j, jal;
- 00053     ac_instr jr, jalr;
- 00054     ac_instr beq, bne, blez, bgtz, bltz, bgez, bltzal, bgezal;
- 00055     ac_instr sys_call, instr_break;
- 00056    
- 00057    
- 00058     // gas MIPS specific register names
- 00059     ac_asm_map reg {
- 00060     "$" [0..31] = [0..31];
- 00061     "$zero" = 0;
- 00062     "$at" = 1;
- 00063     "$kt" [0..1] = [26..27];
- 00064     "$gp" = 28;
- 00065     "$sp" = 29;
- 00066     "$fp" = 30;
- 00067     "$ra" = 31;
- 00068     }
- 00069    
- 00070     ISA_CTOR (mips1){
- 00071    
- 00072     lb.set_asm ("lb %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00073     lb.set_asm ("lb %reg, (%reg)" , rt, rs, imm=0);
- 00074     lb.set_asm ("lb %reg, %imm (%reg)" , rt, imm, rs);
- 00075     lb.set_decoder (op=0x20);
- 00076    
- 00077     lbu.set_asm ("lbu %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00078     lbu.set_asm ("lbu %reg, (%reg)" , rt, rs, imm=0);
- 00079     lbu.set_asm ("lbu %reg, %imm (%reg)" , rt, imm, rs);
- 00080     lbu.set_decoder (op=0x24);
- 00081    
- 00082     lh.set_asm ("lh %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00083     lh.set_asm ("lh %reg, (%reg)" , rt, rs, imm=0);
- 00084     lh.set_asm ("lh %reg, %imm (%reg)" , rt, imm, rs);
- 00085     lh.set_decoder (op=0x21);
- 00086    
- 00087     lhu.set_asm ("lhu %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00088     lhu.set_asm ("lhu %reg, (%reg)" , rt, rs, imm=0);
- 00089     lhu.set_asm ("lhu %reg, %imm (%reg)" , rt, imm, rs);
- 00090     lhu.set_decoder (op=0x25);
- 00091    
- 00092     lw.set_asm ("lw %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00093     lw.set_asm ("lw %reg, (%reg)" , rt, rs, imm=0);
- 00094     lw.set_asm ("lw %reg, %imm (%reg)" , rt, imm, rs);
- 00095     lw.set_decoder (op=0x23);
- 00096    
- 00097     lwl.set_asm ("lwl %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00098     lwl.set_asm ("lwl %reg, (%reg)" , rt, rs, imm=0);
- 00099     lwl.set_asm ("lwl %reg, %imm (%reg)" , rt, imm, rs);
- 00100     lwl.set_decoder (op=0x22);
- 00101    
- 00102     lwr.set_asm ("lwr %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00103     lwr.set_asm ("lwr %reg, (%reg)" , rt, rs, imm=0);
- 00104     lwr.set_asm ("lwr %reg, %imm (%reg)" , rt, imm, rs);
- 00105     lwr.set_decoder (op=0x26);
- 00106    
- 00107     sb.set_asm ("sb %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00108     sb.set_asm ("sb %reg, (%reg)" , rt, rs, imm=0);
- 00109     sb.set_asm ("sb %reg, %imm (%reg)" , rt, imm, rs);
- 00110     sb.set_decoder (op=0x28);
- 00111    
- 00112     sh.set_asm ("sh %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00113     sh.set_asm ("sh %reg, (%reg)" , rt, rs, imm=0);
- 00114     sh.set_asm ("sh %reg, %imm (%reg)" , rt, imm, rs);
- 00115     sh.set_decoder (op=0x29);
- 00116    
- 00117     sw.set_asm ("sw %reg, \%lo(%exp)(%reg)" , rt, imm, rs);
- 00118     sw.set_asm ("sw %reg, (%reg)" , rt, rs, imm=0);
- 00119     sw.set_asm ("sw %reg, %imm (%reg)" , rt, imm, rs);
- 00120     sw.set_decoder (op=0x2B);
- 00121    
- 00122     swl.set_asm ("swl %reg, (%reg)" , rt, rs, imm=0);
- 00123     swl.set_asm ("swl %reg, %imm (%reg)" , rt, imm, rs);
- 00124     swl.set_decoder (op=0x2A);
- 00125    
- 00126     swr.set_asm ("swr %reg, (%reg)" , rt, rs, imm=0);
- 00127     swr.set_asm ("swr %reg, %imm (%reg)" , rt, imm, rs);
- 00128     swr.set_decoder (op=0x2E);
- 00129    
- 00130     addi.set_asm ("addi %reg, %reg, %exp" , rt, rs, imm);
- 00131     addi.set_asm ("add %reg, %reg, %exp" , rt, rs, imm);
- 00132     addi.set_decoder (op=0x08);
- 00133    
- 00134     addiu.set_asm ("addiu %reg, %reg, %exp" , rt, rs, imm);
- 00135     addiu.set_asm ("addiu %reg, %reg, \%lo(%exp)" , rt, rs, imm);
- 00136     addiu.set_asm ("addu %reg, %reg, %exp" , rt, rs, imm);
- 00137     addiu.set_decoder (op=0x09);
- 00138    
- 00139     slti.set_asm ("slti %reg, %reg, %exp" , rt, rs, imm);
- 00140     slti.set_asm ("slt %reg, %reg, %exp" , rt, rs, imm);
- 00141     slti.set_decoder (op=0x0A);
- 00142    
- 00143     sltiu.set_asm ("sltiu %reg, %reg, %exp" , rt, rs, imm);
- 00144     sltiu.set_asm ("sltu %reg, %reg, %exp" , rt, rs, imm);
- 00145     sltiu.set_decoder (op=0x0B);
- 00146    
- 00147     andi.set_asm ("andi %reg, %reg, %imm" , rt, rs, imm);
- 00148     andi.set_asm ("and %reg, %reg, %imm" , rt, rs, imm);
- 00149     andi.set_decoder (op=0x0C);
- 00150    
- 00151     ori.set_asm ("ori %reg, %reg, %imm" , rt, rs, imm);
- 00152     ori.set_asm ("or %reg, %reg, %imm" , rt, rs, imm);
- 00153     ori.set_decoder (op=0x0D);
- 00154    
- 00155     xori.set_asm ("xori %reg, %reg, %imm" , rt, rs, imm);
- 00156     xori.set_asm ("xor %reg, %reg, %imm" , rt, rs, imm);
- 00157     xori.set_decoder (op=0x0E);
- 00158    
- 00159     lui.set_asm ("lui %reg, %exp" , rt, imm);
- 00160     lui.set_asm ("lui %reg, \%hi(%imm(carry))" , rt, imm);
- 00161     lui.set_asm ("lui %reg, \%hi(%exp(carry))" , rt, imm);
- 00162     lui.set_decoder (op=0x0F, rs=0x00);
- 00163    
- 00164     add.set_asm ("add %reg, %reg, %reg" , rd, rs, rt);
- 00165     add.set_decoder (op=0x00, func=0x20);
- 00166    
- 00167     addu.set_asm ("addu %reg, %reg, %reg" , rd, rs, rt);
- 00168     addu.set_asm ("move %reg, %reg" , rd, rs, rt="$zero");
- 00169     addu.set_decoder (op=0x00, func=0x21);
- 00170    
- 00171     sub.set_asm ("sub %reg, %reg, %reg" , rd, rs, rt);
- 00172     sub.set_decoder (op=0x00, func=0x22);
- 00173    
- 00174     subu.set_asm ("subu %reg, %reg, %reg" , rd, rs, rt);
- 00175     subu.set_decoder (op=0x00, func=0x23);
- 00176    
- 00177     slt.set_asm ("slt %reg, %reg, %reg" , rd, rs, rt);
- 00178     slt.set_decoder (op=0x00, func=0x2A);
- 00179    
- 00180     sltu.set_asm ("sltu %reg, %reg, %reg" , rd, rs, rt);
- 00181     sltu.set_decoder (op=0x00, func=0x2B);
- 00182    
- 00183     instr_and.set_asm ("and %reg, %reg, %reg" , rd, rs, rt);
- 00184     instr_and.set_decoder (op=0x00, func=0x24);
- 00185    
- 00186     instr_or.set_asm ("or %reg, %reg, %reg" , rd, rs, rt);
- 00187     instr_or.set_decoder (op=0x00, func=0x25);
- 00188    
- 00189     instr_xor.set_asm ("xor %reg, %reg, %reg" , rd, rs, rt);
- 00190     instr_xor.set_decoder (op=0x00, func=0x26);
- 00191    
- 00192     instr_nor.set_asm ("nor %reg, %reg, %reg" , rd, rs, rt);
- 00193     instr_nor.set_decoder (op=0x00, func=0x27);
- 00194    
- 00195     nop.set_asm ("nop" , rs=0, rt=0, shamt=0);
- 00196     nop.set_decoder (op=0x00, rd=0x00, func=0x00);
- 00197    
- 00198     sll.set_asm ("sll %reg, %reg, %imm" , rd, rt, shamt);
- 00199     sll.set_decoder (op=0x00, func= 0x00);
- 00200    
- 00201     srl.set_asm ("srl %reg, %reg, %imm" , rd, rt, shamt);
- 00202     srl.set_decoder (op=0x00, func= 0x02);
- 00203    
- 00204     sra.set_asm ("sra %reg, %reg, %imm" , rd, rt, shamt);
- 00205     sra.set_decoder (op=0x00, func= 0x03);
- 00206    
- 00207     sllv.set_asm ("sllv %reg, %reg, %reg" , rd, rt, rs);
- 00208     sllv.set_asm ("sll %reg, %reg, %reg" , rd, rt, rs); // gas
- 00209     sllv.set_decoder (op=0x00, func= 0x04);
- 00210    
- 00211     srlv.set_asm ("srlv %reg, %reg, %reg" , rd, rt, rs);
- 00212     srlv.set_asm ("srl %reg, %reg, %reg" , rd, rt, rs); // gas
- 00213     srlv.set_decoder (op=0x00, func= 0x06);
- 00214    
- 00215     srav.set_asm ("srav %reg, %reg, %reg" , rd, rt, rs);
- 00216     srav.set_asm ("sra %reg, %reg, %reg" , rd, rt, rs); // gas
- 00217     srav.set_decoder (op=0x00, func= 0x07);
- 00218    
- 00219     mult.set_asm ("mult %reg, %reg" , rs, rt);
- 00220     mult.set_decoder (op=0x00, func=0x18);
- 00221    
- 00222     multu.set_asm ("multu %reg, %reg" , rs, rt);
- 00223     multu.set_decoder (op=0x00, func=0x19);
- 00224    
- 00225     div.set_asm ("div %reg, %reg" , rs, rt);
- 00226     div.set_decoder (op=0x00, func=0x1A);
- 00227    
- 00228     divu.set_asm ("divu %reg, %reg" , rs, rt);
- 00229     divu.set_decoder (op=0x00, func=0x1B);
- 00230    
- 00231     mfhi.set_asm ("mfhi %reg" , rd);
- 00232     mfhi.set_decoder (op=0x00, func=0x10);
- 00233    
- 00234     mthi.set_asm ("mthi %reg" , rs);
- 00235     mthi.set_decoder (op=0x00, func=0x11);
- 00236    
- 00237     mflo.set_asm ("mflo %reg" , rd);
- 00238     mflo.set_decoder (op=0x00, func=0x12);
- 00239    
- 00240     mtlo.set_asm ("mtlo %reg" , rs);
- 00241     mtlo.set_decoder (op=0x00, func=0x13);
- 00242    
- 00243     j.set_asm ("j %exp(align)" , addr);
- 00244     j.set_decoder (op=0x02);
- 00245    
- 00246     jal.set_asm ("jal %exp(align)" , addr);
- 00247     jal.set_decoder (op=0x03);
- 00248    
- 00249     jr.set_asm ("jr %reg" , rs);
- 00250     jr.set_asm ("j %reg" , rs);
- 00251     jr.set_asm ("ret" , rs = "$ra");
- 00252     jr.set_decoder (op=0x00, func= 0x08);
- 00253    
- 00254     jalr.set_asm ("jalr %reg, %reg" , rd, rs);
- 00255     jalr.set_asm ("jalr %reg" , rs, rd="$ra");
- 00256     jalr.set_asm ("jal %reg" , rs, rd="$ra"); // gas
- 00257     jalr.set_decoder (op=0x00, func= 0x09);
- 00258    
- 00259     beq.set_asm ("beq %reg, %reg, %exp(pcrel)" , rs, rt, imm);
- 00260     beq.set_asm ("b %exp(pcrel)" , imm, rs=0, rt=0); // gas
- 00261     beq.set_asm ("beqz %reg, %exp(pcrel)" , rs, imm, rt=0); // gas
- 00262     beq.set_decoder (op=0x04);
- 00263    
- 00264     bne.set_asm ("bgtu %reg, $0, %exp(pcrel)" , rs, imm, rt=0x00); // bgtu with second operand fixed in 0
- 00265     bne.set_asm ("bne %reg, %reg, %exp(pcrel)" , rs, rt, imm);
- 00266     bne.set_asm ("bnez %reg, %exp(pcrel)" , rs, imm, rt=0);
- 00267     bne.set_decoder (op=0x05);
- 00268    
- 00269     blez.set_asm ("blez %reg, %exp(pcrel)" , rs, imm);
- 00270     blez.set_decoder (op=0x06, rt=0x00);
- 00271    
- 00272     bgtz.set_asm ("bgtz %reg, %exp(pcrel)" , rs, imm);
- 00273     bgtz.set_decoder (op=0x07, rt=0x00);
- 00274    
- 00275     bltz.set_asm ("bltz %reg, %exp(pcrel)" , rs, imm);
- 00276     bltz.set_decoder (op=0x01, rt=0x00);
- 00277    
- 00278     bgez.set_asm ("bgez %reg, %exp(pcrel)" , rs, imm);
- 00279     bgez.set_decoder (op=0x01, rt=0x01);
- 00280    
- 00281     bltzal.set_asm ("bltzal %reg, %exp(pcrel)" , rs, imm);
- 00282     bltzal.set_decoder (op=0x01, rt=0x10);
- 00283    
- 00284     bgezal.set_asm ("bgezal %reg, %exp(pcrel)" , rs, imm);
- 00285     bgezal.set_decoder (op=0x01, rt=0x11);
- 00286    
- 00287     sys_call.set_asm ("syscall" );
- 00288     sys_call.set_decoder (op=0x00, func=0x0C);
- 00289    
- 00290     instr_break.set_asm ("break" , rt=0);
- 00291     instr_break.set_asm ("break %imm" , rt);
- 00292     instr_break.set_decoder (op=0x00, func=0x0D);
- 00293    
- 00294    
- 00295     pseudo_instr ("li %reg, %imm" ) {
- 00296     "lui %0, \%hi(%1)" ;
- 00297     "ori %0, %0, %1" ;
- 00298     }
- 00299    
- 00300     pseudo_instr ("la %reg, %addr" ) {
- 00301     "lui %0, \%hi(%1)" ;
- 00302     "addiu %0, %0, \%lo(%1)" ;
- 00303     }
- 00304    
- 00305     pseudo_instr ("sw %reg, %exp" ) {
- 00306     "lui $at, \%hi(%1)" ;
- 00307     "sw %0, \%lo(%1)($at)" ;
- 00308     }
- 00309    
- 00310     pseudo_instr ("lw %reg, %exp" ) {
- 00311     "lui %0, \%hi(%1)" ;
- 00312     "lw %0, \%lo(%1)(%0)" ;
- 00313     }
- 00314    
- 00315     pseudo_instr ("subu %reg, %reg, %imm" ) {
- 00316     "addiu %0, %1, -%2" ;
- 00317     }
- 00318    
- 00319     pseudo_instr ("ble %reg, %reg, %exp" ) {
- 00320     "slt $at, %1, %0" ;
- 00321     "beq $at, $zero, %2" ;
- 00322     }
- 00323    
- 00324     pseudo_instr ("ble %reg, %imm, %exp" ) {
- 00325     "slti $at, %0, %1+1" ;
- 00326     "bne $at, $zero, %2" ;
- 00327     }
- 00328    
- 00329     pseudo_instr ("mul %reg, %reg, %reg" ) {
- 00330     "multu %1, %2" ;
- 00331     "mflo %0" ;
- 00332     }
- 00333    
- 00334     pseudo_instr ("bge %reg, %reg, %exp" ) {
- 00335     "slt $at, %0, %1" ;
- 00336     "beq $at, $zero, %2" ;
- 00337     }
- 00338    
- 00339     pseudo_instr ("bgt %reg, %imm, %exp" ) {
- 00340     "slti $at, %0, %1+1" ;
- 00341     "beq $at, $zero, %2" ;
- 00342     }
- 00343    
- 00344     pseudo_instr ("mul %reg, %reg, %imm" ) {
- 00345     "addiu $at, $zero, %2" ;
- 00346     "mult %1, $at" ;
- 00347     "mflo %0" ;
- 00348     }
- 00349    
- 00350     pseudo_instr ("lw %reg, %exp (%reg)" ) {
- 00351     /* this should be 'li %0, %1', but 'li' is a conditional pseudo in gas :/
- 00352     - this only works when %exp < 2^16-1 - should be enough for validation */
- 00353     "lui %0, %1" ;
- 00354     "addu %0, %0, %2" ;
- 00355     "lw %0, (%0)" ;
- 00356     }
- 00357    
- 00358     pseudo_instr ("sw %reg, %exp (%reg)" ) {
- 00359     /* this should be 'li %0, %1', but 'li' is a conditional pseudo in gas :/
- 00360     - this only works when %exp < 2^16-1 - should be enough for validation */
- 00361     "lui $at, %1" ;
- 00362     "addu $at, $at, %2" ;
- 00363     "sw %0, ($at)" ;
- 00364     }
- 00365    
- 00366     pseudo_instr ("bne %reg, %imm, %exp" ) {
- 00367     "addiu $at, $zero, %1" ;
- 00368     "bne %0, $at, %2" ;
- 00369     }
- 00370    
- 00371    
- 00372     /*******************************************************/
- 00373     /* Optional properties to optimize compiled simulation */
- 00374     /*******************************************************/
- 00375    
- 00376     j.is_jump (((ac_pc+4) & 0xF0000000) | (addr<<2));
- 00377     j.delay (1);
- 00378    
- 00379     jal.is_jump (((ac_pc+4) & 0xF0000000) | (addr<<2));
- 00380     jal.delay (1);
- 00381     jal.behavior (RB[31] = (ac_pc+4)+4;);
- 00382    
- 00383     jr.is_jump (RB[rs]);
- 00384     jr.delay (1);
- 00385    
- 00386     jalr.is_jump (RB[rs]);
- 00387     jalr.delay (1);
- 00388     jalr.behavior (RB[(rd==0)?31:rd] = (ac_pc+4)+4;);
- 00389    
- 00390     beq.is_branch ((ac_pc+4) + (imm<<2));
- 00391     beq.cond (RB[rs] == RB[rt]);
- 00392     beq.delay (1);
- 00393    
- 00394     bne.is_branch ((ac_pc+4) + (imm<<2));
- 00395     bne.cond (RB[rs] != RB[rt]);
- 00396     bne.delay (1);
- 00397    
- 00398     blez.is_branch ((ac_pc+4) + (imm<<2));
- 00399     blez.cond ((RB[rs] == 0 ) || (RB[rs]&0x80000000 ));
- 00400     blez.delay (1);
- 00401    
- 00402     bgtz.is_branch ((ac_pc+4) + (imm<<2));
- 00403     bgtz.cond (!(RB[rs] & 0x80000000) && (RB[rs]!=0));
- 00404     bgtz.delay (1);
- 00405    
- 00406     bltz.is_branch ((ac_pc+4) + (imm<<2));
- 00407     bltz.cond (RB[rs] & 0x80000000);
- 00408     bltz.delay (1);
- 00409    
- 00410     bgez.is_branch ((ac_pc+4) + (imm<<2));
- 00411     bgez.cond (!(RB[rs] & 0x80000000));
- 00412     bgez.delay (1);
- 00413    
- 00414     bltzal.is_branch ((ac_pc+4) + (imm<<2));
- 00415     bltzal.cond (RB[rs] & 0x80000000);
- 00416     bltzal.delay (1);
- 00417    
- 00418     bgezal.is_branch ((ac_pc+4) + (imm<<2));
- 00419     bgezal.cond (!(RB[rs] & 0x80000000));
- 00420     bgezal.delay (1);
- 00421    
- 00422     };
- 00423    
- 00424     };