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- 00001     /**
- 00002     * @file IA32.ac
- 00003     * @author Rodolfo Jardim de Azevedo
- 00004     * Valdiney Alves Pimenta
- 00005     * Team 03 - MC723 - 2005, 1st period
- 00006     * Eduardo Uemura Okada
- 00007     * Andre Deiano Pansani
- 00008     * Ricardo Andrade
- 00009     *
- 00010     * The ArchC Team
- 00011     * http://www.archc.org/
- 00012     *
- 00013     * Computer Systems Laboratory (LSC)
- 00014     * IC-UNICAMP
- 00015     * http://www.lsc.ic.unicamp.br
- 00016     *
- 00017     * @version 1.0
- 00018     * @date Thu, 29 Jun 2006 14:49:06 -0300
- 00019     *
- 00020     * @brief The ArchC x86 functional model.
- 00021     *
- 00022     * @attention Copyright (C) 2002-2006 --- The ArchC Team
- 00023     *
- 00024     */
- 00025    
- 00026     // Assumpmitions:
- 00027     //
- 00028     // Memory is treated as processor internal as of this functional model. And no
- 00029     // caching is emulated.
- 00030     //
- 00031     // No segment register override is implemented yet.
- 00032    
- 00033     AC_ARCH (IA32)
- 00034     {
- 00035     // IA32 Family word is 16bit-wide, but registers are 32bits in this model
- 00036     ac_wordsize 32;
- 00037    
- 00038     // Memory is internal in this functional model
- 00039     ac_mem MEM:32M;
- 00040    
- 00041     // General purpose registers (32bit registers) :
- 00042     // EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI
- 00043     ac_regbank GR:8;
- 00044    
- 00045     // Segment registers (segment registers are 16bit-wide):
- 00046     // CS, DS, SS, ES, FS, GS
- 00047     ac_regbank SR:6;
- 00048    
- 00049     // Special registers (32bit registers) :
- 00050     // EFLAGS, EIP
- 00051     ac_regbank SPR:2;
- 00052    
- 00053     ARCH_CTOR (IA32)
- 00054     {
- 00055     ac_isa ("IA32_isa.ac" );
- 00056     set_endian ("little" );
- 00057     };
- 00058     };
- 00059