fpu_adder_conf Project Status | |||
Project File: | fpu_core.xise | Parser Errors: | No Errors |
Module Name: | fpu_adder_conf | Implementation State: | Synthesized |
Target Device: | xc5vlx330-1ff1760 |
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No Errors |
Product Version: | ISE 14.7 |
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19 Warnings (19 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 14 | 207360 | 0% | |
Number of Slice LUTs | 26 | 207360 | 0% | |
Number of fully used LUT-FF pairs | 12 | 28 | 42% | |
Number of bonded IOBs | 43 | 1200 | 3% | |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ti 25. mar 15:49:11 2014 | 0 | 19 Warnings (19 new) | 17 Infos (17 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | fr 28. mar 15:12:07 2014 |