configurable_divider Project Status (05/22/2014 - 13:20:35)
Project File: fpu_core.xise Parser Errors: No Errors
Module Name: configurable_divider Implementation State: Synthesized
Target Device: xc5vlx330-2ff1760
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentma 19. mai 17:47:06 2014   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Dateto 22. mai 10:43:45 2014

Date Generated: 05/22/2014 - 13:20:35