configurable_divider Project Status (05/22/2014 - 13:20:35) | |||
Project File: | fpu_core.xise | Parser Errors: | No Errors |
Module Name: | configurable_divider | Implementation State: | Synthesized |
Target Device: | xc5vlx330-2ff1760 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ma 19. mai 17:47:06 2014 | ||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | to 22. mai 10:43:45 2014 |