configurable_adder_unsigned Project Status (06/03/2014 - 17:23:49)
Project File: fpu_core.xise Parser Errors: No Errors
Module Name: configurable_adder_unsigned Implementation State: Synthesized
Target Device: xc5vlx330-2ff1760
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Dateti 3. jun 16:29:24 2014

Date Generated: 06/03/2014 - 17:24:00