fpu_adder_conf Project Status
Project File: fpu_core.xise Parser Errors: No Errors
Module Name: fpu_adder_conf Implementation State: Synthesized
Target Device: xc5vlx330-1ff1760
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
19 Warnings (19 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 14 207360 0%
Number of Slice LUTs 26 207360 0%
Number of fully used LUT-FF pairs 12 28 42%
Number of bonded IOBs 43 1200 3%
Number of BUFG/BUFGCTRLs 1 32 3%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentti 25. mar 15:49:11 2014019 Warnings (19 new)17 Infos (17 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentfr 28. mar 15:12:07 2014

Date Generated: 04/01/2014 - 10:11:39