my_custom_ip_register Project Status
Project File: my_custom_ip_register.xise Parser Errors: No Errors
Module Name: my_custom_ip_register Implementation State: Synthesized
Target Device: xc5vlx50-1ff676
  • Errors:
No Errors
Product Version:ISE 12.1
  • Warnings:
406 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 121 28800 0%
Number of Slice LUTs 100 28800 0%
Number of fully used LUT-FF pairs 48 173 27%
Number of bonded IOBs 230 440 52%
Number of BUFG/BUFGCTRLs 1 32 3%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Jun 8 21:54:20 20100406 Warnings (1 new)4 Infos (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 06/09/2010 - 20:08:55