BSCAN_BSCAN
DSP48E
- ALUMODE0=[ALUMODE0:5] [ALUMODE0_INV:0]
- ALUMODE1=[ALUMODE1:5] [ALUMODE1_INV:0]
- ALUMODE2=[ALUMODE2:5] [ALUMODE2_INV:0]
- ALUMODE3=[ALUMODE3:5] [ALUMODE3_INV:0]
- CARRYIN=[CARRYIN:5] [CARRYIN_INV:0]
- CLK=[CLK:5] [CLK_INV:0]
- OPMODE0=[OPMODE0:5] [OPMODE0_INV:0]
- OPMODE1=[OPMODE1_INV:0] [OPMODE1:5]
- OPMODE2=[OPMODE2:5] [OPMODE2_INV:0]
- OPMODE3=[OPMODE3:5] [OPMODE3_INV:0]
- OPMODE4=[OPMODE4:5] [OPMODE4_INV:0]
- OPMODE5=[OPMODE5_INV:0] [OPMODE5:5]
- OPMODE6=[OPMODE6_INV:0] [OPMODE6:5]
DSP48E_DSP48E
- ACASCREG=[0:4] [1:1]
- ALUMODE0=[ALUMODE0:5] [ALUMODE0_INV:0]
- ALUMODE1=[ALUMODE1:5] [ALUMODE1_INV:0]
- ALUMODE2=[ALUMODE2:5] [ALUMODE2_INV:0]
- ALUMODE3=[ALUMODE3:5] [ALUMODE3_INV:0]
- ALUMODEREG=[0:5]
- AREG=[0:4] [1:1]
- AUTORESET_OVER_UNDER_FLOW=[FALSE:5]
- AUTORESET_PATTERN_DETECT=[FALSE:5]
- AUTORESET_PATTERN_DETECT_OPTINV=[MATCH:5]
- A_INPUT=[DIRECT:5]
- BCASCREG=[0:4] [1:1]
- BREG=[0:4] [1:1]
- B_INPUT=[DIRECT:5]
- CARRYIN=[CARRYIN:5] [CARRYIN_INV:0]
- CARRYINREG=[0:5]
- CARRYINSELREG=[0:5]
- CLK=[CLK:5] [CLK_INV:0]
- CLOCK_INVERT_M=[SAME_EDGE:5]
- CLOCK_INVERT_P=[SAME_EDGE:5]
- CREG=[0:5]
- LFSR_EN_SET=[SET:5]
- LFSR_EN_SETVAL=[0:5]
- MREG=[0:1] [1:4]
- MULTCARRYINREG=[0:5]
- OPMODE0=[OPMODE0:5] [OPMODE0_INV:0]
- OPMODE1=[OPMODE1_INV:0] [OPMODE1:5]
- OPMODE2=[OPMODE2:5] [OPMODE2_INV:0]
- OPMODE3=[OPMODE3:5] [OPMODE3_INV:0]
- OPMODE4=[OPMODE4:5] [OPMODE4_INV:0]
- OPMODE5=[OPMODE5_INV:0] [OPMODE5:5]
- OPMODE6=[OPMODE6_INV:0] [OPMODE6:5]
- OPMODEREG=[0:5]
- PREG=[0:2] [1:3]
- ROUNDING_LSB_MASK=[0:5]
- SCAN_IN_SETVAL_M=[0:5]
- SCAN_IN_SETVAL_P=[0:5]
- SCAN_IN_SET_M=[SET:5]
- SCAN_IN_SET_P=[SET:5]
- SEL_MASK=[MASK:5]
- SEL_PATTERN=[PATTERN:5]
- SEL_ROUNDING_MASK=[SEL_MASK:5]
- TEST_SETVAL_M=[0:5]
- TEST_SETVAL_P=[0:5]
- TEST_SET_M=[SET:5]
- TEST_SET_P=[SET:5]
- USE_MULT=[MULT_S:4] [MULT:1]
- USE_PATTERN_DETECT=[NO_PATDET:3] [PATDET:2]
- USE_SIMD=[ONE48:5]
ILOGIC
ILOGIC_IFF
- CK=[CK:18] [CK_INV:0]
- IFFTYPE=[FF:18]
- INIT_Q1=[0:17] [1:1]
- SRTYPE=[ASYNC:16] [SYNC:2]
- SRVAL_Q1=[0:16] [1:2]
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IOB_PULL
OLOGIC
- CLK=[CLK:27] [CLK_INV:0]
- D1=[D1:26] [D1_INV:1]
- T1=[T1_INV:0] [T1:16]
OLOGIC_OUTFF
- CK=[CK:27] [CK_INV:0]
- D1=[D1:26] [D1_INV:1]
- INIT_OQ=[0:23] [1:4]
- OUTFFTYPE=[FF:27]
- SRTYPE_OQ=[ASYNC:26] [SYNC:1]
- SRVAL_OQ=[0:23] [1:4]
OLOGIC_TFF
- CK=[CK:16] [CK_INV:0]
- D1=[D1:16] [D1_INV:0]
- INIT_TQ=[1:16]
- SRTYPE_TQ=[ASYNC:16]
- SRVAL_TQ=[1:16]
- TFFTYPE=[FF:16]
PLL_ADV
- CLKINSEL=[CLKINSEL:1] [CLKINSEL_INV:0]
- REL=[REL_INV:0] [REL:1]
- RST=[RST:1] [RST_INV:0]
PLL_ADV_PLL_ADV
- BANDWIDTH=[OPTIMIZED:1]
- CLKFBOUT_DESKEW_ADJUST=[0:1]
- CLKINSEL=[CLKINSEL:1] [CLKINSEL_INV:0]
- CLKOUT0_DESKEW_ADJUST=[0:1]
- CLKOUT1_DESKEW_ADJUST=[0:1]
- CLKOUT2_DESKEW_ADJUST=[0:1]
- CLKOUT3_DESKEW_ADJUST=[0:1]
- CLKOUT4_DESKEW_ADJUST=[0:1]
- CLKOUT5_DESKEW_ADJUST=[0:1]
- CMT_TEST_CLK_SEL=[7:1]
- COMPENSATION=[SYSTEM_SYNCHRONOUS:1]
- DIVCLK_DIVIDE=[1:1]
- EN_REL=[FALSE:1]
- LOCK_FAST_FILTER=[HIGH:1]
- LOCK_SLOW_FILTER=[HIGH:1]
- PLL_2_DCM1_CLK_SEL=[6:1]
- PLL_2_DCM2_CLK_SEL=[6:1]
- PLL_AVDD_COMP_SET=[3:1]
- PLL_AVDD_VBG_PD=[1:1]
- PLL_AVDD_VBG_SEL=[9:1]
- PLL_CLK0MX=[0:1]
- PLL_CLK1MX=[0:1]
- PLL_CLK2MX=[0:1]
- PLL_CLK3MX=[0:1]
- PLL_CLK4MX=[0:1]
- PLL_CLK5MX=[0:1]
- PLL_CLKBURST_CNT=[0:1]
- PLL_CLKBURST_ENABLE=[FALSE:1]
- PLL_CLKCNTRL=[0:1]
- PLL_CLKFBMX=[0:1]
- PLL_CLKFBOUT2_EDGE=[TRUE:1]
- PLL_CLKFBOUT2_NOCOUNT=[TRUE:1]
- PLL_CLKFB_MUX_SEL=[0:1]
- PLL_CLKIN_MUX_SEL=[0:1]
- PLL_CP_BIAS_TRIP_SHIFT=[FALSE:1]
- PLL_CP_RES=[1:1]
- PLL_DIRECT_PATH_CNTRL=[FALSE:1]
- PLL_DVDD_COMP_SET=[3:1]
- PLL_DVDD_VBG_PD=[1:1]
- PLL_DVDD_VBG_SEL=[9:1]
- PLL_EN=[FALSE:1]
- PLL_EN_TCLK0=[FALSE:1]
- PLL_EN_TCLK1=[FALSE:1]
- PLL_EN_TCLK2=[FALSE:1]
- PLL_EN_TCLK3=[FALSE:1]
- PLL_EN_TCLK4=[FALSE:1]
- PLL_EN_VCO0=[TRUE:1]
- PLL_EN_VCO1=[TRUE:1]
- PLL_EN_VCO2=[TRUE:1]
- PLL_EN_VCO3=[TRUE:1]
- PLL_EN_VCO4=[TRUE:1]
- PLL_EN_VCO5=[TRUE:1]
- PLL_EN_VCO6=[TRUE:1]
- PLL_EN_VCO7=[TRUE:1]
- PLL_EN_VCO_DIV1=[FALSE:1]
- PLL_EN_VCO_DIV6=[FALSE:1]
- PLL_INC_FLOCK=[TRUE:1]
- PLL_INC_SLOCK=[TRUE:1]
- PLL_LF_NEN=[3:1]
- PLL_LF_PEN=[0:1]
- PLL_LOCK_CNT=[63:1]
- PLL_LOCK_CNT_RST_FAST=[FALSE:1]
- PLL_MAN_LF_EN=[FALSE:1]
- PLL_NBTI_EN=[FALSE:1]
- PLL_PFD_CNTRL=[8:1]
- PLL_PFD_DLY=[1:1]
- PLL_PMCD_MODE=[FALSE:1]
- PLL_PWRD_CFG=[FALSE:1]
- PLL_SEL_SLIPD=[FALSE:1]
- PLL_SKEW_CNTRL=[0:1]
- PLL_TCK4_SEL=[0:1]
- PLL_UNLOCK_CNT=[4:1]
- PLL_UNLOCK_CNT_RST_FAST=[FALSE:1]
- PLL_VLFHIGH_DIS=[FALSE:1]
- REL=[REL_INV:0] [REL:1]
- RESET_ON_LOSS_OF_LOCK=[FALSE:1]
- RST=[RST:1] [RST_INV:0]
- RST_DEASSERT_CLK=[CLKIN1:1]
- WAIT_DCM1_LOCK=[FALSE:1]
- WAIT_DCM2_LOCK=[FALSE:1]
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RAMB36_EXP
- CLKAL=[CLKAL_INV:0] [CLKAL:32]
- CLKAU=[CLKAU:32] [CLKAU_INV:0]
- CLKBL=[CLKBL:32] [CLKBL_INV:0]
- CLKBU=[CLKBU:32] [CLKBU_INV:0]
- ENAL=[ENAL_INV:0] [ENAL:32]
- ENAU=[ENAU_INV:0] [ENAU:32]
- ENBL=[ENBL_INV:0] [ENBL:32]
- ENBU=[ENBU_INV:0] [ENBU:32]
- REGCLKAL=[REGCLKAL:0] [REGCLKAL_INV:32]
- REGCLKAU=[REGCLKAU_INV:32] [REGCLKAU:0]
- REGCLKBL=[REGCLKBL_INV:32] [REGCLKBL:0]
- REGCLKBU=[REGCLKBU_INV:32] [REGCLKBU:0]
- SSRAL=[SSRAL:32] [SSRAL_INV:0]
- SSRAU=[SSRAU:32] [SSRAU_INV:0]
- SSRBL=[SSRBL:32] [SSRBL_INV:0]
- SSRBU=[SSRBU:32] [SSRBU_INV:0]
RAMB36_EXP_RAMB36_EXP
- CLKAL=[CLKAL_INV:0] [CLKAL:32]
- CLKAU=[CLKAU:32] [CLKAU_INV:0]
- CLKBL=[CLKBL:32] [CLKBL_INV:0]
- CLKBU=[CLKBU:32] [CLKBU_INV:0]
- DOA_REG=[0:32]
- DOB_REG=[0:32]
- ENAL=[ENAL_INV:0] [ENAL:32]
- ENAU=[ENAU_INV:0] [ENAU:32]
- ENBL=[ENBL_INV:0] [ENBL:32]
- ENBU=[ENBU_INV:0] [ENBU:32]
- RAM_EXTENSION_A=[NONE:32]
- RAM_EXTENSION_B=[NONE:32]
- READ_WIDTH_A=[1:32]
- READ_WIDTH_B=[1:32]
- REGCLKAL=[REGCLKAL:0] [REGCLKAL_INV:32]
- REGCLKAU=[REGCLKAU_INV:32] [REGCLKAU:0]
- REGCLKBL=[REGCLKBL_INV:32] [REGCLKBL:0]
- REGCLKBU=[REGCLKBU_INV:32] [REGCLKBU:0]
- SAVEDATA=[FALSE:32]
- SSRAL=[SSRAL:32] [SSRAL_INV:0]
- SSRAU=[SSRAU:32] [SSRAU_INV:0]
- SSRBL=[SSRBL:32] [SSRBL_INV:0]
- SSRBU=[SSRBU:32] [SSRBU_INV:0]
- WRITE_MODE_A=[WRITE_FIRST:32]
- WRITE_MODE_B=[WRITE_FIRST:32]
- WRITE_WIDTH_A=[1:32]
- WRITE_WIDTH_B=[1:32]
SLICEL
- CLK=[CLK:1005] [CLK_INV:5]
SLICEL_AFF
- AFFINIT=[INIT0:719] [INIT1:30]
- AFFSR=[SRLOW:720] [SRHIGH:29]
- CK=[CK:746] [CK_INV:3]
- LATCH_OR_FF=[FF:749]
- SYNC_ATTR=[ASYNC:173] [SYNC:576]
SLICEL_BFF
- BFFINIT=[INIT0:637] [INIT1:26]
- BFFSR=[SRLOW:637] [SRHIGH:26]
- CK=[CK:661] [CK_INV:2]
- LATCH_OR_FF=[FF:663]
- SYNC_ATTR=[ASYNC:169] [SYNC:494]
SLICEL_CFF
- CFFINIT=[INIT0:551] [INIT1:20]
- CFFSR=[SRLOW:549] [SRHIGH:21]
- CK=[CK:568] [CK_INV:3]
- LATCH_OR_FF=[FF:570] [LATCH:1]
- SYNC_ATTR=[ASYNC:144] [SYNC:427]
SLICEL_DFF
- CK=[CK:597] [CK_INV:3]
- DFFINIT=[INIT0:577] [INIT1:23]
- DFFSR=[SRLOW:576] [SRHIGH:23]
- LATCH_OR_FF=[FF:599] [LATCH:1]
- SYNC_ATTR=[ASYNC:148] [SYNC:452]
SLICEM
SLICEM_A5LUT
- A5RAMMODE=[SRL16:1] [DPRAM32:21]
- CLK=[CLK:22] [CLK_INV:0]
- LUT_OR_MEM=[LUT:1] [RAM:22]
SLICEM_A6LUT
- A6RAMMODE=[SRL16:39] [DPRAM32:21] [DPRAM64:1]
- CLK=[CLK:61] [CLK_INV:0]
- LUT_OR_MEM=[LUT:1] [RAM:61]
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SLICEM_AFF
- AFFINIT=[INIT0:20] [INIT1:3]
- AFFSR=[SRLOW:20] [SRHIGH:3]
- CK=[CK:23] [CK_INV:0]
- LATCH_OR_FF=[FF:23]
- SYNC_ATTR=[ASYNC:18] [SYNC:5]
SLICEM_B5LUT
- B5RAMMODE=[DPRAM32:21]
- CLK=[CLK:21] [CLK_INV:0]
- LUT_OR_MEM=[LUT:1] [RAM:21]
SLICEM_B6LUT
- B6RAMMODE=[SRL16:21] [DPRAM32:21] [DPRAM64:1]
- CLK=[CLK:43] [CLK_INV:0]
- LUT_OR_MEM=[LUT:9] [RAM:43]
SLICEM_BFF
- BFFINIT=[INIT0:12]
- BFFSR=[SRLOW:12]
- CK=[CK:12] [CK_INV:0]
- LATCH_OR_FF=[FF:12]
- SYNC_ATTR=[ASYNC:11] [SYNC:1]
SLICEM_C5LUT
- C5RAMMODE=[DPRAM32:21]
- CLK=[CLK:21] [CLK_INV:0]
- LUT_OR_MEM=[LUT:1] [RAM:21]
SLICEM_C6LUT
- C6RAMMODE=[SRL16:16] [DPRAM32:21] [DPRAM64:1]
- CLK=[CLK:38] [CLK_INV:0]
- LUT_OR_MEM=[LUT:8] [RAM:38]
SLICEM_CFF
- CFFINIT=[INIT0:14]
- CFFSR=[SRLOW:14]
- CK=[CK:14] [CK_INV:0]
- LATCH_OR_FF=[FF:14]
- SYNC_ATTR=[ASYNC:13] [SYNC:1]
SLICEM_D5LUT
- CLK=[CLK:21] [CLK_INV:0]
- D5RAMMODE=[DPRAM32:21]
- LUT_OR_MEM=[LUT:1] [RAM:21]
SLICEM_D6LUT
- CLK=[CLK:33] [CLK_INV:0]
- D6RAMMODE=[SRL16:11] [DPRAM32:21] [DPRAM64:1]
- LUT_OR_MEM=[LUT:5] [RAM:33]
SLICEM_DFF
- CK=[CK:4] [CK_INV:0]
- DFFINIT=[INIT0:4]
- DFFSR=[SRLOW:4]
- LATCH_OR_FF=[FF:4]
- SYNC_ATTR=[ASYNC:4]
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