Name |
Value |
C_FAMILY Family
|
virtex5 |
C_SPEEDGRADE Speed Grade
|
-1 |
C_EXT_RESET_HIGH External Reset
|
0 |
C_CLK_GEN C_CLK_GEN
|
update |
C_CLKOUT0_MODULE C_CLKOUT0_MODULE
|
NONE |
C_CLKOUT0_PORT C_CLKOUT0_PORT
|
NONE |
C_CLKOUT1_MODULE C_CLKOUT1_MODULE
|
NONE |
C_CLKOUT1_PORT C_CLKOUT1_PORT
|
NONE |
C_CLKOUT2_MODULE C_CLKOUT2_MODULE
|
NONE |
C_CLKOUT2_PORT C_CLKOUT2_PORT
|
NONE |
C_CLKOUT3_MODULE C_CLKOUT3_MODULE
|
NONE |
C_CLKOUT3_PORT C_CLKOUT3_PORT
|
NONE |
C_CLKOUT4_MODULE C_CLKOUT4_MODULE
|
NONE |
C_CLKOUT4_PORT C_CLKOUT4_PORT
|
NONE |
C_CLKOUT5_MODULE C_CLKOUT5_MODULE
|
NONE |
C_CLKOUT5_PORT C_CLKOUT5_PORT
|
NONE |
C_CLKOUT6_MODULE C_CLKOUT6_MODULE
|
NONE |
C_CLKOUT6_PORT C_CLKOUT6_PORT
|
NONE |
C_CLKOUT7_MODULE C_CLKOUT7_MODULE
|
NONE |
C_CLKOUT7_PORT C_CLKOUT7_PORT
|
NONE |
C_CLKOUT8_MODULE C_CLKOUT8_MODULE
|
NONE |
C_CLKOUT8_PORT C_CLKOUT8_PORT
|
NONE |
C_CLKOUT9_MODULE C_CLKOUT9_MODULE
|
NONE |
C_CLKOUT9_PORT C_CLKOUT9_PORT
|
NONE |
C_CLKOUT10_MODULE C_CLKOUT10_MODULE
|
NONE |
C_CLKOUT10_PORT C_CLKOUT10_PORT
|
NONE |
C_CLKOUT11_MODULE C_CLKOUT11_MODULE
|
NONE |
C_CLKOUT11_PORT C_CLKOUT11_PORT
|
NONE |
C_CLKOUT12_MODULE C_CLKOUT12_MODULE
|
NONE |
C_CLKOUT12_PORT C_CLKOUT12_PORT
|
NONE |
C_CLKOUT13_MODULE C_CLKOUT13_MODULE
|
NONE |
C_CLKOUT13_PORT C_CLKOUT13_PORT
|
NONE |
C_CLKOUT14_MODULE C_CLKOUT14_MODULE
|
NONE |
C_CLKOUT14_PORT C_CLKOUT14_PORT
|
NONE |
C_CLKOUT15_MODULE C_CLKOUT15_MODULE
|
NONE |
C_CLKOUT15_PORT C_CLKOUT15_PORT
|
NONE |
C_CLKFBOUT_MODULE C_CLKFBOUT_MODULE
|
NONE |
C_CLKFBOUT_PORT C_CLKFBOUT_PORT
|
NONE |
C_PSDONE_MODULE C_PSDONE_MODULE
|
NONE |
C_PLL0_DIVCLK_DIVIDE C_PLL0_DIVCLK_DIVIDE
|
1 |
C_PLL0_CLKFBOUT_MULT C_PLL0_CLKFBOUT_MULT
|
1 |
C_PLL0_CLKFBOUT_PHASE C_PLL0_CLKFBOUT_PHASE
|
0.000000 |
C_PLL0_CLKIN1_PERIOD C_PLL0_CLKIN1_PERIOD
|
0.000000 |
C_PLL0_CLKOUT0_DIVIDE C_PLL0_CLKOUT0_DIVIDE
|
1 |
C_PLL0_CLKOUT0_DUTY_CYCLE C_PLL0_CLKOUT0_DUTY_CYCLE
|
0.500000 |
C_PLL0_CLKOUT0_PHASE C_PLL0_CLKOUT0_PHASE
|
0.000000 |
C_PLL0_CLKOUT1_DIVIDE C_PLL0_CLKOUT1_DIVIDE
|
1 |
C_PLL0_CLKOUT1_DUTY_CYCLE C_PLL0_CLKOUT1_DUTY_CYCLE
|
0.500000 |
C_PLL0_CLKOUT1_PHASE C_PLL0_CLKOUT1_PHASE
|
0.000000 |
C_PLL0_CLKOUT2_DIVIDE C_PLL0_CLKOUT2_DIVIDE
|
1 |
C_PLL0_CLKOUT2_DUTY_CYCLE C_PLL0_CLKOUT2_DUTY_CYCLE
|
0.500000 |
C_PLL0_CLKOUT2_PHASE C_PLL0_CLKOUT2_PHASE
|
0.000000 |
C_PLL0_CLKOUT3_DIVIDE C_PLL0_CLKOUT3_DIVIDE
|
1 |
C_PLL0_CLKOUT3_DUTY_CYCLE C_PLL0_CLKOUT3_DUTY_CYCLE
|
0.500000 |
C_PLL0_CLKOUT3_PHASE C_PLL0_CLKOUT3_PHASE
|
0.000000 |
C_PLL0_CLKOUT4_DIVIDE C_PLL0_CLKOUT4_DIVIDE
|
1 |
C_PLL0_CLKOUT4_DUTY_CYCLE C_PLL0_CLKOUT4_DUTY_CYCLE
|
0.500000 |
C_PLL0_CLKOUT4_PHASE C_PLL0_CLKOUT4_PHASE
|
0.000000 |
C_PLL0_CLKOUT5_DIVIDE C_PLL0_CLKOUT5_DIVIDE
|
1 |
C_PLL0_CLKOUT5_DUTY_CYCLE C_PLL0_CLKOUT5_DUTY_CYCLE
|
0.500000 |
C_PLL0_CLKOUT5_PHASE C_PLL0_CLKOUT5_PHASE
|
0.000000 |
C_PLL0_BANDWIDTH C_PLL0_BANDWIDTH
|
OPTIMIZED |
C_PLL0_COMPENSATION C_PLL0_COMPENSATION
|
SYSTEM_SYNCHRONOUS |
C_PLL0_REF_JITTER C_PLL0_REF_JITTER
|
0.100000 |
C_PLL0_RESET_ON_LOSS_OF_LOCK C_PLL0_RESET_ON_LOSS_OF_LOCK
|
false |
C_PLL0_RST_DEASSERT_CLK C_PLL0_RST_DEASSERT_CLK
|
CLKIN1 |
C_PLL0_EXT_RESET_HIGH C_PLL0_EXT_RESET_HIGH
|
1 |
C_PLL0_FAMILY C_PLL0_FAMILY
|
virtex5 |
C_PLL0_CLKOUT0_DESKEW_ADJUST C_PLL0_CLKOUT0_DESKEW_ADJUST
|
NONE |
C_PLL0_CLKOUT1_DESKEW_ADJUST C_PLL0_CLKOUT1_DESKEW_ADJUST
|
NONE |
C_PLL0_CLKOUT2_DESKEW_ADJUST C_PLL0_CLKOUT2_DESKEW_ADJUST
|
NONE |
C_PLL0_CLKOUT3_DESKEW_ADJUST C_PLL0_CLKOUT3_DESKEW_ADJUST
|
NONE |
C_PLL0_CLKOUT4_DESKEW_ADJUST C_PLL0_CLKOUT4_DESKEW_ADJUST
|
NONE |
C_PLL0_CLKOUT5_DESKEW_ADJUST C_PLL0_CLKOUT5_DESKEW_ADJUST
|
NONE |
C_PLL0_CLKFBOUT_DESKEW_ADJUST C_PLL0_CLKFBOUT_DESKEW_ADJUST
|
NONE |
C_PLL0_CLKIN1_BUF C_PLL0_CLKIN1_BUF
|
false |
C_PLL0_CLKFBOUT_BUF C_PLL0_CLKFBOUT_BUF
|
false |
C_PLL0_CLKOUT0_BUF C_PLL0_CLKOUT0_BUF
|
false |
C_PLL0_CLKOUT1_BUF C_PLL0_CLKOUT1_BUF
|
false |
C_PLL0_CLKOUT2_BUF C_PLL0_CLKOUT2_BUF
|
false |
C_PLL0_CLKOUT3_BUF C_PLL0_CLKOUT3_BUF
|
false |
C_PLL0_CLKOUT4_BUF C_PLL0_CLKOUT4_BUF
|
false |
C_PLL0_CLKOUT5_BUF C_PLL0_CLKOUT5_BUF
|
false |
C_PLL0_CLKIN1_MODULE C_PLL0_CLKIN1_MODULE
|
NONE |
C_PLL0_CLKIN1_PORT C_PLL0_CLKIN1_PORT
|
NONE |
C_PLL0_CLKFBIN_MODULE C_PLL0_CLKFBIN_MODULE
|
NONE |
C_PLL0_CLKFBIN_PORT C_PLL0_CLKFBIN_PORT
|
NONE |
C_PLL0_RST_MODULE C_PLL0_RST_MODULE
|
NONE |
C_PLL1_DIVCLK_DIVIDE C_PLL1_DIVCLK_DIVIDE
|
1 |
C_PLL1_CLKFBOUT_MULT C_PLL1_CLKFBOUT_MULT
|
1 |
C_PLL1_CLKFBOUT_PHASE C_PLL1_CLKFBOUT_PHASE
|
0.000000 |
C_PLL1_CLKIN1_PERIOD C_PLL1_CLKIN1_PERIOD
|
0.000000 |
C_PLL1_CLKOUT0_DIVIDE C_PLL1_CLKOUT0_DIVIDE
|
1 |
C_PLL1_CLKOUT0_DUTY_CYCLE C_PLL1_CLKOUT0_DUTY_CYCLE
|
0.500000 |
C_PLL1_CLKOUT0_PHASE C_PLL1_CLKOUT0_PHASE
|
0.000000 |
C_PLL1_CLKOUT1_DIVIDE C_PLL1_CLKOUT1_DIVIDE
|
1 |
C_PLL1_CLKOUT1_DUTY_CYCLE C_PLL1_CLKOUT1_DUTY_CYCLE
|
0.500000 |
C_PLL1_CLKOUT1_PHASE C_PLL1_CLKOUT1_PHASE
|
0.000000 |
C_PLL1_CLKOUT2_DIVIDE C_PLL1_CLKOUT2_DIVIDE
|
1 |
C_PLL1_CLKOUT2_DUTY_CYCLE C_PLL1_CLKOUT2_DUTY_CYCLE
|
0.500000 |
C_PLL1_CLKOUT2_PHASE C_PLL1_CLKOUT2_PHASE
|
0.000000 |
C_PLL1_CLKOUT3_DIVIDE C_PLL1_CLKOUT3_DIVIDE
|
1 |
C_PLL1_CLKOUT3_DUTY_CYCLE C_PLL1_CLKOUT3_DUTY_CYCLE
|
0.500000 |
C_PLL1_CLKOUT3_PHASE C_PLL1_CLKOUT3_PHASE
|
0.000000 |
C_PLL1_CLKOUT4_DIVIDE C_PLL1_CLKOUT4_DIVIDE
|
1 |
C_PLL1_CLKOUT4_DUTY_CYCLE C_PLL1_CLKOUT4_DUTY_CYCLE
|
0.500000 |
C_PLL1_CLKOUT4_PHASE C_PLL1_CLKOUT4_PHASE
|
0.000000 |
C_PLL1_CLKOUT5_DIVIDE C_PLL1_CLKOUT5_DIVIDE
|
1 |
C_PLL1_CLKOUT5_DUTY_CYCLE C_PLL1_CLKOUT5_DUTY_CYCLE
|
0.500000 |
C_PLL1_CLKOUT5_PHASE C_PLL1_CLKOUT5_PHASE
|
0.000000 |
C_PLL1_BANDWIDTH C_PLL1_BANDWIDTH
|
OPTIMIZED |
C_PLL1_COMPENSATION C_PLL1_COMPENSATION
|
SYSTEM_SYNCHRONOUS |
C_PLL1_REF_JITTER C_PLL1_REF_JITTER
|
0.100000 |
C_PLL1_RESET_ON_LOSS_OF_LOCK C_PLL1_RESET_ON_LOSS_OF_LOCK
|
false |
C_PLL1_RST_DEASSERT_CLK C_PLL1_RST_DEASSERT_CLK
|
CLKIN1 |
C_PLL1_EXT_RESET_HIGH C_PLL1_EXT_RESET_HIGH
|
1 |
C_PLL1_FAMILY C_PLL1_FAMILY
|
virtex5 |
C_PLL1_CLKOUT0_DESKEW_ADJUST C_PLL1_CLKOUT0_DESKEW_ADJUST
|
NONE |
C_PLL1_CLKOUT1_DESKEW_ADJUST C_PLL1_CLKOUT1_DESKEW_ADJUST
|
NONE |
C_PLL1_CLKOUT2_DESKEW_ADJUST C_PLL1_CLKOUT2_DESKEW_ADJUST
|
NONE |
C_PLL1_CLKOUT3_DESKEW_ADJUST C_PLL1_CLKOUT3_DESKEW_ADJUST
|
NONE |
C_PLL1_CLKOUT4_DESKEW_ADJUST C_PLL1_CLKOUT4_DESKEW_ADJUST
|
NONE |
C_PLL1_CLKOUT5_DESKEW_ADJUST C_PLL1_CLKOUT5_DESKEW_ADJUST
|
NONE |
C_PLL1_CLKFBOUT_DESKEW_ADJUST C_PLL1_CLKFBOUT_DESKEW_ADJUST
|
NONE |
C_PLL1_CLKIN1_BUF C_PLL1_CLKIN1_BUF
|
false |
C_PLL1_CLKFBOUT_BUF C_PLL1_CLKFBOUT_BUF
|
false |
C_PLL1_CLKOUT0_BUF C_PLL1_CLKOUT0_BUF
|
false |
C_PLL1_CLKOUT1_BUF C_PLL1_CLKOUT1_BUF
|
false |
C_PLL1_CLKOUT2_BUF C_PLL1_CLKOUT2_BUF
|
false |
C_PLL1_CLKOUT3_BUF C_PLL1_CLKOUT3_BUF
|
false |
C_PLL1_CLKOUT4_BUF C_PLL1_CLKOUT4_BUF
|
false |
C_PLL1_CLKOUT5_BUF C_PLL1_CLKOUT5_BUF
|
false |
C_PLL1_CLKIN1_MODULE C_PLL1_CLKIN1_MODULE
|
NONE |
C_PLL1_CLKIN1_PORT C_PLL1_CLKIN1_PORT
|
NONE |
C_PLL1_CLKFBIN_MODULE C_PLL1_CLKFBIN_MODULE
|
NONE |
C_PLL1_CLKFBIN_PORT C_PLL1_CLKFBIN_PORT
|
NONE |
C_PLL1_RST_MODULE C_PLL1_RST_MODULE
|
NONE |
C_DCM0_DFS_FREQUENCY_MODE C_DCM0_DFS_FREQUENCY_MODE
|
LOW |
C_DCM0_DLL_FREQUENCY_MODE C_DCM0_DLL_FREQUENCY_MODE
|
LOW |
C_DCM0_DUTY_CYCLE_CORRECTION C_DCM0_DUTY_CYCLE_CORRECTION
|
true |
C_DCM0_CLKIN_DIVIDE_BY_2 C_DCM0_CLKIN_DIVIDE_BY_2
|
false |
C_DCM0_CLK_FEEDBACK C_DCM0_CLK_FEEDBACK
|
1X |
C_DCM0_CLKOUT_PHASE_SHIFT C_DCM0_CLKOUT_PHASE_SHIFT
|
NONE |
C_DCM0_DSS_MODE C_DCM0_DSS_MODE
|
NONE |
C_DCM0_STARTUP_WAIT C_DCM0_STARTUP_WAIT
|
false |
C_DCM0_PHASE_SHIFT C_DCM0_PHASE_SHIFT
|
0 |
C_DCM0_CLKFX_MULTIPLY C_DCM0_CLKFX_MULTIPLY
|
4 |
C_DCM0_CLKFX_DIVIDE C_DCM0_CLKFX_DIVIDE
|
1 |
C_DCM0_CLKDV_DIVIDE C_DCM0_CLKDV_DIVIDE
|
2.000000 |
C_DCM0_CLKIN_PERIOD C_DCM0_CLKIN_PERIOD
|
0.000000 |
C_DCM0_DESKEW_ADJUST C_DCM0_DESKEW_ADJUST
|
SYSTEM_SYNCHRONOUS |
C_DCM0_CLKIN_BUF C_DCM0_CLKIN_BUF
|
false |
C_DCM0_CLKFB_BUF C_DCM0_CLKFB_BUF
|
false |
C_DCM0_CLK0_BUF C_DCM0_CLK0_BUF
|
false |
C_DCM0_CLK90_BUF C_DCM0_CLK90_BUF
|
false |
C_DCM0_CLK180_BUF C_DCM0_CLK180_BUF
|
false |
C_DCM0_CLK270_BUF C_DCM0_CLK270_BUF
|
false |
C_DCM0_CLKDV_BUF C_DCM0_CLKDV_BUF
|
false |
C_DCM0_CLKDV180_BUF C_DCM0_CLKDV180_BUF
|
false |
C_DCM0_CLK2X_BUF C_DCM0_CLK2X_BUF
|
false |
C_DCM0_CLK2X180_BUF C_DCM0_CLK2X180_BUF
|
false |
C_DCM0_CLKFX_BUF C_DCM0_CLKFX_BUF
|
false |
C_DCM0_CLKFX180_BUF C_DCM0_CLKFX180_BUF
|
false |
C_DCM0_EXT_RESET_HIGH C_DCM0_EXT_RESET_HIGH
|
1 |
C_DCM0_FAMILY C_DCM0_FAMILY
|
virtex5 |
C_DCM0_CLKIN_MODULE C_DCM0_CLKIN_MODULE
|
NONE |
C_DCM0_CLKIN_PORT C_DCM0_CLKIN_PORT
|
NONE |
C_DCM0_CLKFB_MODULE C_DCM0_CLKFB_MODULE
|
NONE |
C_DCM0_CLKFB_PORT C_DCM0_CLKFB_PORT
|
NONE |
C_DCM0_RST_MODULE C_DCM0_RST_MODULE
|
NONE |
C_DCM1_DFS_FREQUENCY_MODE C_DCM1_DFS_FREQUENCY_MODE
|
LOW |
C_DCM1_DLL_FREQUENCY_MODE C_DCM1_DLL_FREQUENCY_MODE
|
LOW |
C_DCM1_DUTY_CYCLE_CORRECTION C_DCM1_DUTY_CYCLE_CORRECTION
|
true |
C_DCM1_CLKIN_DIVIDE_BY_2 C_DCM1_CLKIN_DIVIDE_BY_2
|
false |
C_DCM1_CLK_FEEDBACK C_DCM1_CLK_FEEDBACK
|
1X |
C_DCM1_CLKOUT_PHASE_SHIFT C_DCM1_CLKOUT_PHASE_SHIFT
|
NONE |
C_DCM1_DSS_MODE C_DCM1_DSS_MODE
|
NONE |
C_DCM1_STARTUP_WAIT C_DCM1_STARTUP_WAIT
|
false |
C_DCM1_PHASE_SHIFT C_DCM1_PHASE_SHIFT
|
0 |
C_DCM1_CLKFX_MULTIPLY C_DCM1_CLKFX_MULTIPLY
|
4 |
C_DCM1_CLKFX_DIVIDE C_DCM1_CLKFX_DIVIDE
|
1 |
C_DCM1_CLKDV_DIVIDE C_DCM1_CLKDV_DIVIDE
|
2.000000 |
C_DCM1_CLKIN_PERIOD C_DCM1_CLKIN_PERIOD
|
0.000000 |
C_DCM1_DESKEW_ADJUST C_DCM1_DESKEW_ADJUST
|
SYSTEM_SYNCHRONOUS |
C_DCM1_CLKIN_BUF C_DCM1_CLKIN_BUF
|
false |
C_DCM1_CLKFB_BUF C_DCM1_CLKFB_BUF
|
false |
C_DCM1_CLK0_BUF C_DCM1_CLK0_BUF
|
false |
C_DCM1_CLK90_BUF C_DCM1_CLK90_BUF
|
false |
C_DCM1_CLK180_BUF C_DCM1_CLK180_BUF
|
false |
C_DCM1_CLK270_BUF C_DCM1_CLK270_BUF
|
false |
C_DCM1_CLKDV_BUF C_DCM1_CLKDV_BUF
|
false |
C_DCM1_CLKDV180_BUF C_DCM1_CLKDV180_BUF
|
false |
C_DCM1_CLK2X_BUF C_DCM1_CLK2X_BUF
|
false |
C_DCM1_CLK2X180_BUF C_DCM1_CLK2X180_BUF
|
false |
C_DCM1_CLKFX_BUF C_DCM1_CLKFX_BUF
|
false |
C_DCM1_CLKFX180_BUF C_DCM1_CLKFX180_BUF
|
false |
C_DCM1_EXT_RESET_HIGH C_DCM1_EXT_RESET_HIGH
|
1 |
C_DCM1_FAMILY C_DCM1_FAMILY
|
virtex5 |
C_DCM1_CLKIN_MODULE C_DCM1_CLKIN_MODULE
|
NONE |
C_DCM1_CLKIN_PORT C_DCM1_CLKIN_PORT
|
NONE |
C_DCM1_CLKFB_MODULE C_DCM1_CLKFB_MODULE
|
NONE |
C_DCM1_CLKFB_PORT C_DCM1_CLKFB_PORT
|
NONE |
C_DCM1_RST_MODULE C_DCM1_RST_MODULE
|
NONE |
C_DCM2_DFS_FREQUENCY_MODE C_DCM2_DFS_FREQUENCY_MODE
|
LOW |
C_DCM2_DLL_FREQUENCY_MODE C_DCM2_DLL_FREQUENCY_MODE
|
LOW |
C_DCM2_DUTY_CYCLE_CORRECTION C_DCM2_DUTY_CYCLE_CORRECTION
|
true |
C_DCM2_CLKIN_DIVIDE_BY_2 C_DCM2_CLKIN_DIVIDE_BY_2
|
false |
C_DCM2_CLK_FEEDBACK C_DCM2_CLK_FEEDBACK
|
1X |
C_DCM2_CLKOUT_PHASE_SHIFT C_DCM2_CLKOUT_PHASE_SHIFT
|
NONE |
C_DCM2_DSS_MODE C_DCM2_DSS_MODE
|
NONE |
C_DCM2_STARTUP_WAIT C_DCM2_STARTUP_WAIT
|
false |
C_DCM2_PHASE_SHIFT C_DCM2_PHASE_SHIFT
|
0 |
C_DCM2_CLKFX_MULTIPLY C_DCM2_CLKFX_MULTIPLY
|
4 |
C_DCM2_CLKFX_DIVIDE C_DCM2_CLKFX_DIVIDE
|
1 |
C_DCM2_CLKDV_DIVIDE C_DCM2_CLKDV_DIVIDE
|
2.000000 |
C_DCM2_CLKIN_PERIOD C_DCM2_CLKIN_PERIOD
|
0.000000 |
C_DCM2_DESKEW_ADJUST C_DCM2_DESKEW_ADJUST
|
SYSTEM_SYNCHRONOUS |
C_DCM2_CLKIN_BUF C_DCM2_CLKIN_BUF
|
false |
C_DCM2_CLKFB_BUF C_DCM2_CLKFB_BUF
|
false |
C_DCM2_CLK0_BUF C_DCM2_CLK0_BUF
|
false |
C_DCM2_CLK90_BUF C_DCM2_CLK90_BUF
|
false |
C_DCM2_CLK180_BUF C_DCM2_CLK180_BUF
|
false |
C_DCM2_CLK270_BUF C_DCM2_CLK270_BUF
|
false |
C_DCM2_CLKDV_BUF C_DCM2_CLKDV_BUF
|
false |
C_DCM2_CLKDV180_BUF C_DCM2_CLKDV180_BUF
|
false |
C_DCM2_CLK2X_BUF C_DCM2_CLK2X_BUF
|
false |
C_DCM2_CLK2X180_BUF C_DCM2_CLK2X180_BUF
|
false |
C_DCM2_CLKFX_BUF C_DCM2_CLKFX_BUF
|
false |
C_DCM2_CLKFX180_BUF C_DCM2_CLKFX180_BUF
|
false |
C_DCM2_EXT_RESET_HIGH C_DCM2_EXT_RESET_HIGH
|
1 |
C_DCM2_FAMILY C_DCM2_FAMILY
|
virtex5 |
C_DCM2_CLKIN_MODULE C_DCM2_CLKIN_MODULE
|
NONE |
C_DCM2_CLKIN_PORT C_DCM2_CLKIN_PORT
|
NONE |
C_DCM2_CLKFB_MODULE C_DCM2_CLKFB_MODULE
|
NONE |
C_DCM2_CLKFB_PORT C_DCM2_CLKFB_PORT
|
NONE |
C_DCM2_RST_MODULE C_DCM2_RST_MODULE
|
NONE |
C_DCM3_DFS_FREQUENCY_MODE C_DCM3_DFS_FREQUENCY_MODE
|
LOW |
C_DCM3_DLL_FREQUENCY_MODE C_DCM3_DLL_FREQUENCY_MODE
|
LOW |
C_DCM3_DUTY_CYCLE_CORRECTION C_DCM3_DUTY_CYCLE_CORRECTION
|
true |
C_DCM3_CLKIN_DIVIDE_BY_2 C_DCM3_CLKIN_DIVIDE_BY_2
|
false |
C_DCM3_CLK_FEEDBACK C_DCM3_CLK_FEEDBACK
|
1X |
C_DCM3_CLKOUT_PHASE_SHIFT C_DCM3_CLKOUT_PHASE_SHIFT
|
NONE |
C_DCM3_DSS_MODE C_DCM3_DSS_MODE
|
NONE |
C_DCM3_STARTUP_WAIT C_DCM3_STARTUP_WAIT
|
false |
C_DCM3_PHASE_SHIFT C_DCM3_PHASE_SHIFT
|
0 |
C_DCM3_CLKFX_MULTIPLY C_DCM3_CLKFX_MULTIPLY
|
4 |
C_DCM3_CLKFX_DIVIDE C_DCM3_CLKFX_DIVIDE
|
1 |
C_DCM3_CLKDV_DIVIDE C_DCM3_CLKDV_DIVIDE
|
2.000000 |
C_DCM3_CLKIN_PERIOD C_DCM3_CLKIN_PERIOD
|
0.000000 |
C_DCM3_DESKEW_ADJUST C_DCM3_DESKEW_ADJUST
|
SYSTEM_SYNCHRONOUS |
C_DCM3_CLKIN_BUF C_DCM3_CLKIN_BUF
|
false |
C_DCM3_CLKFB_BUF C_DCM3_CLKFB_BUF
|
false |
C_DCM3_CLK0_BUF C_DCM3_CLK0_BUF
|
false |
C_DCM3_CLK90_BUF C_DCM3_CLK90_BUF
|
false |
C_DCM3_CLK180_BUF C_DCM3_CLK180_BUF
|
false |
C_DCM3_CLK270_BUF C_DCM3_CLK270_BUF
|
false |
C_DCM3_CLKDV_BUF C_DCM3_CLKDV_BUF
|
false |
C_DCM3_CLKDV180_BUF C_DCM3_CLKDV180_BUF
|
false |
C_DCM3_CLK2X_BUF C_DCM3_CLK2X_BUF
|
false |
C_DCM3_CLK2X180_BUF C_DCM3_CLK2X180_BUF
|
false |
C_DCM3_CLKFX_BUF C_DCM3_CLKFX_BUF
|
false |
C_DCM3_CLKFX180_BUF C_DCM3_CLKFX180_BUF
|
false |
C_DCM3_EXT_RESET_HIGH C_DCM3_EXT_RESET_HIGH
|
1 |
C_DCM3_FAMILY C_DCM3_FAMILY
|
virtex5 |
C_DCM3_CLKIN_MODULE C_DCM3_CLKIN_MODULE
|
NONE |
C_DCM3_CLKIN_PORT C_DCM3_CLKIN_PORT
|
NONE |
C_DCM3_CLKFB_MODULE C_DCM3_CLKFB_MODULE
|
NONE |
C_DCM3_CLKFB_PORT C_DCM3_CLKFB_PORT
|
NONE |
C_DCM3_RST_MODULE C_DCM3_RST_MODULE
|
NONE |
C_MMCM0_BANDWIDTH C_MMCM0_BANDWIDTH
|
OPTIMIZED |
C_MMCM0_CLKFBOUT_MULT_F C_MMCM0_CLKFBOUT_MULT_F
|
1.000000 |
C_MMCM0_CLKFBOUT_PHASE C_MMCM0_CLKFBOUT_PHASE
|
0.000000 |
C_MMCM0_CLKFBOUT_USE_FINE_PS C_MMCM0_CLKFBOUT_USE_FINE_PS
|
false |
C_MMCM0_CLKIN1_PERIOD C_MMCM0_CLKIN1_PERIOD
|
0.000000 |
C_MMCM0_CLKOUT0_DIVIDE_F C_MMCM0_CLKOUT0_DIVIDE_F
|
1.000000 |
C_MMCM0_CLKOUT0_DUTY_CYCLE C_MMCM0_CLKOUT0_DUTY_CYCLE
|
0.500000 |
C_MMCM0_CLKOUT0_PHASE C_MMCM0_CLKOUT0_PHASE
|
0.000000 |
C_MMCM0_CLKOUT1_DIVIDE C_MMCM0_CLKOUT1_DIVIDE
|
1 |
C_MMCM0_CLKOUT1_DUTY_CYCLE C_MMCM0_CLKOUT1_DUTY_CYCLE
|
0.500000 |
C_MMCM0_CLKOUT1_PHASE C_MMCM0_CLKOUT1_PHASE
|
0.000000 |
C_MMCM0_CLKOUT2_DIVIDE C_MMCM0_CLKOUT2_DIVIDE
|
1 |
C_MMCM0_CLKOUT2_DUTY_CYCLE C_MMCM0_CLKOUT2_DUTY_CYCLE
|
0.500000 |
C_MMCM0_CLKOUT2_PHASE C_MMCM0_CLKOUT2_PHASE
|
0.000000 |
C_MMCM0_CLKOUT3_DIVIDE C_MMCM0_CLKOUT3_DIVIDE
|
1 |
C_MMCM0_CLKOUT3_DUTY_CYCLE C_MMCM0_CLKOUT3_DUTY_CYCLE
|
0.500000 |
C_MMCM0_CLKOUT3_PHASE C_MMCM0_CLKOUT3_PHASE
|
0.000000 |
C_MMCM0_CLKOUT4_DIVIDE C_MMCM0_CLKOUT4_DIVIDE
|
1 |
C_MMCM0_CLKOUT4_DUTY_CYCLE C_MMCM0_CLKOUT4_DUTY_CYCLE
|
0.500000 |
C_MMCM0_CLKOUT4_PHASE C_MMCM0_CLKOUT4_PHASE
|
0.000000 |