Printable Version
Overview
Resources Used
1   MicroBlaze
1   Processor Local Bus (PLB) 4.6
2   Local Memory Bus (LMB) 1.0
1   Block RAM (BRAM) Block
2   LMB BRAM Controller
1   XPS Interrupt Controller
1   Processor System Reset Module
1   MicroBlaze Debug Module (MDM)
1   Clock Generator
1   XPS System ACE Interface Controller(Compact Flash)
1   XPS UART (Lite)
Specifics
Generated Thu May 20 22:32:55 2010
EDK Version 12.1
Device Family virtex5
Device xc5vlx50ff676-1

Block Diagram TOP

BlockDiagram
External Ports TOP

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
SHARED fpga_0_rst_1_sys_rst_pin I 1 sys_rst_s  RESET 
RS232_Uart fpga_0_RS232_Uart_RX_pin I 1 fpga_0_RS232_Uart_RX_pin
RS232_Uart fpga_0_RS232_Uart_TX_pin O 1 fpga_0_RS232_Uart_TX_pin
SysACE_CompactFlash fpga_0_SysACE_CompactFlash_SysACE_CLK_pin I 1 fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
SysACE_CompactFlash fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin I 1 fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
SysACE_CompactFlash fpga_0_SysACE_CompactFlash_SysACE_MPD_pin IO 15:0 fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
SysACE_CompactFlash fpga_0_SysACE_CompactFlash_SysACE_CEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
SysACE_CompactFlash fpga_0_SysACE_CompactFlash_SysACE_MPA_pin O 6:0 fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
SysACE_CompactFlash fpga_0_SysACE_CompactFlash_SysACE_OEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
SysACE_CompactFlash fpga_0_SysACE_CompactFlash_SysACE_WEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
clock_generator_0 fpga_0_clk_1_sys_clk_pin I 1 dcm_clk_s  CLK 


Processors TOP

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor

IP Specs
Core Version Documentation
microblaze 7.30.a IP


microblaze_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_RESET I 1 mb_reset
1 INTERRUPT I 1 xps_intc_0_Irq
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
DLMB MASTER LMB dlmb dlmb_cntlr
ILMB MASTER LMB ilmb ilmb_cntlr
DPLB MASTER PLBV46 mb_plb 5 Peripherals.
IPLB MASTER PLBV46 mb_plb 5 Peripherals.
DEBUG TARGET XIL_MBDEBUG2 microblaze_0_mdm_bus mdm_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SCO 0
C_FREQ 125000000
C_DATA_SIZE 32
C_DYNAMIC_BUS_SIZING 1
C_FAMILY virtex5
C_INSTANCE microblaze_0
C_AREA_OPTIMIZED
Select implementation to optimize area (with lower instruction throughput)
0
C_OPTIMIZATION 0
C_INTERCONNECT
Select Bus Interfaces
1
C_DPLB_DWIDTH 32
C_DPLB_NATIVE_DWIDTH 32
C_DPLB_BURST_EN 0
C_DPLB_P2P 0
C_IPLB_DWIDTH 32
C_IPLB_NATIVE_DWIDTH 32
C_IPLB_BURST_EN 0
C_IPLB_P2P 0
C_D_PLB 0
C_D_LMB 1
C_I_PLB 0
C_I_LMB 1
C_USE_MSR_INSTR
Enable Additional Machine Status Register Instructions
1
C_USE_PCMP_INSTR
Enable Pattern Comparator
1
C_USE_BARREL
Enable Barrel Shifter
0
C_USE_DIV
Enable Integer Divider
0
C_USE_HW_MUL
Enable Integer Multiplier
1
C_USE_FPU
Enable Floating Point Unit
1
C_UNALIGNED_EXCEPTIONS
Enable Unaligned Data Exception
0
C_ILL_OPCODE_EXCEPTION
Enable Illegal Instruction Exception
0
C_IPLB_BUS_EXCEPTION
Enable Instruction-side PLB Exception
0
C_DPLB_BUS_EXCEPTION
Enable Data-side PLB Exception
0
C_DIV_ZERO_EXCEPTION
Enable Integer Divide Exception
0
C_FPU_EXCEPTION
Enable Floating Point Unit Exceptions
0
C_FSL_EXCEPTION
Enable FSL Exception
0
C_PVR
Specifies Processor Version Register
0
C_PVR_USER1
Specify USER1 Bits in Processor Version Register
0x00
C_PVR_USER2
Specify USER2 Bits in Processor Version Registers
0x00000000
C_DEBUG_ENABLED
Enable MicroBlaze Debug Module Interface
1
C_NUMBER_OF_PC_BRK
Number of PC Breakpoints
1
C_NUMBER_OF_RD_ADDR_BRK
Number of Read Address Watchpoints
0
C_NUMBER_OF_WR_ADDR_BRK
Number of Write Address Watchpoints
0
 
Name Value
C_INTERRUPT_IS_EDGE
Sense Interrupt on Edge vs. Level
0
C_EDGE_IS_POSITIVE
Sense Interrupt on Rising vs. Falling Edge
1
C_RESET_MSR
Specify Reset Value for Select MSR Bits
0x00000000
C_OPCODE_0x0_ILLEGAL
<qt>Generate Illegal Instruction Exception for NULL Instruction</qt>
0
C_FSL_LINKS
Number of FSL Links
0
C_FSL_DATA_SIZE 32
C_USE_EXTENDED_FSL_INSTR
Enable Additional FSL Instructions
0
C_ICACHE_BASEADDR
I-Cache Base Address
0x00000000
C_ICACHE_HIGHADDR
I-Cache High Address
0x3FFFFFFF
C_USE_ICACHE
Enable Instruction Cache
0
C_ALLOW_ICACHE_WR
Enable I-Cache Writes
1
C_ADDR_TAG_BITS 17
C_CACHE_BYTE_SIZE
Size of the I-Cache in Bytes
8192
C_ICACHE_USE_FSL 1
C_ICACHE_LINE_LEN
Instruction Cache Line Length
4
C_ICACHE_ALWAYS_USED
Use Cache Links for All I-Cache Memory Accesses
0
C_ICACHE_INTERFACE 0
C_ICACHE_VICTIMS
Number of I-Cache Victims
0
C_ICACHE_STREAMS
Number of I-Cache Streams
0
C_DCACHE_BASEADDR
D-Cache Base Address
0x00000000
C_DCACHE_HIGHADDR
D-Cache High Address
0x3FFFFFFF
C_USE_DCACHE
Enable Data Cache
0
C_ALLOW_DCACHE_WR
Enable D-Cache Writes
1
C_DCACHE_ADDR_TAG 17
C_DCACHE_BYTE_SIZE
Size of D-Cache in Bytes
8192
C_DCACHE_USE_FSL 1
C_DCACHE_LINE_LEN
Data Cache Line Length
4
C_DCACHE_ALWAYS_USED
Use Cache Links for All D-Cache Memory Accesses
0
C_DCACHE_INTERFACE 0
C_DCACHE_USE_WRITEBACK
Enable Write-back Storage Policy
0
C_DCACHE_VICTIMS
Number of D-Cache Victims
0
C_USE_MMU
Memory Management
0
C_MMU_DTLB_SIZE
Data Shadow Translation Look-Aside Buffer Size
4
C_MMU_ITLB_SIZE
Instruction Shadow Translation Look-Aside Buffer Size
2
C_MMU_TLB_ACCESS
Enable Access to Memory Management Special Registers
3
C_MMU_ZONES
Number of Memory Protection Zones
16
C_USE_INTERRUPT 0
C_USE_EXT_BRK 0
C_USE_EXT_NM_BRK 0
C_USE_BRANCH_TARGET_CACHE
Enable Branch Target Cache
0
C_BRANCH_TARGET_CACHE_SIZE
Branch Target Cache Size
0
MEMORY MAP
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
D I BASE HIGH MODULE
  0x00000000 0x0001FFFF C_BASEADDR:C_HIGHADDRdlmb_cntlr
  0x00000000 0x0001FFFF C_BASEADDR:C_HIGHADDRilmb_cntlr
0x81800000 0x8180FFFF C_BASEADDR:C_HIGHADDRxps_intc_0
0x83600000 0x8360FFFF C_BASEADDR:C_HIGHADDRSysACE_CompactFlash
0x84000000 0x8400FFFF C_BASEADDR:C_HIGHADDRRS232_Uart
0x84400000 0x8440FFFF C_BASEADDR:C_HIGHADDRmdm_0
0xCCC00000 0xCCC0FFFF C_BASEADDR:C_HIGHADDRmy_custom_ip_register_0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 1797 28800 6
Slice LUTs 1965 28800 6
LUT Flip Flop pairs used 2914 NA NA
fully used LUT-FF pairs 848 2914 29
unique control sets 116 NA NA
IOs 2296 NA NA
bonded IOBs 0 440 0
DSP48Es 5 48 10




Debuggers TOP

mdm_0   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

IP Specs
Core Version Documentation
mdm 1.00.g IP


mdm_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Debug_SYS_Rst O 1 Debug_SYS_Rst
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MBDEBUG_0 INITIATOR XIL_MBDEBUG2 microblaze_0_mdm_bus microblaze_0
SPLB SLAVE PLBV46 mb_plb 5 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
virtex5
C_JTAG_CHAIN
Specifies the JTAG user-defined register used
2
C_INTERCONNECT
Specifies the Bus Interface for the JTAG UART
1
C_BASEADDR
Base Address
0x84400000
C_HIGHADDR
High Address
0x8440ffff
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
 
Name Value
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_OPB_DWIDTH
OPB Data Bus Width
32
C_OPB_AWIDTH
OPB Address Bus Width
32
C_MB_DBG_PORTS
Number of MicroBlaze debug ports
1
C_USE_UART
Enable JTAG UART
1
C_UART_WIDTH
UART Data size
8
C_WRITE_FSL_PORTS
Enable Write FSL Port
0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 119 28800 0
Slice LUTs 117 28800 0
LUT Flip Flop pairs used 193 NA NA
fully used LUT-FF pairs 43 193 22
unique control sets 31 NA NA
IOs 498 NA NA
bonded IOBs 0 440 0
BUFG/BUFGCTRLs 2 32 6




Interrupt Controllers TOP

xps_intc_0   XPS Interrupt Controller
intc core attached to the PLBV46

IP Specs
Core Version Documentation
xps_intc 2.01.a IP


xps_intc_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Irq O 1 xps_intc_0_Irq
1 Intr I 0:1 my_custom_ip_register_0_IP2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 5 Peripherals.
Interrupt Priorities
Priority SIG MODULE
0 my_custom_ip_register_0_IP2INTC_Irpt my_custom_ip_register_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
virtex5
C_BASEADDR
Base Address
0x81800000
C_HIGHADDR
High Address
0x8180ffff
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
 
Name Value
C_NUM_INTR_INPUTS
Number of Interrupt Inputs
2
C_KIND_OF_INTR
Type of Interrupt for Each Input
0xffffffff
C_KIND_OF_EDGE
Type of Each Edge Senstive Interrupt
0xffffffff
C_KIND_OF_LVL
Type of Each Level Sensitive Interrupt
0xffffffff
C_HAS_IPR
Support IPR
1
C_HAS_SIE
Support SIE
1
C_HAS_CIE
Support CIE
1
C_HAS_IVR
Support IVR
1
C_IRQ_IS_LEVEL
IRQ Output Use Level
1
C_IRQ_ACTIVE
The Sense of IRQ Output
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 116 28800 0
Slice LUTs 78 28800 0
LUT Flip Flop pairs used 148 NA NA
fully used LUT-FF pairs 46 148 31
unique control sets 29 NA NA
IOs 203 NA NA
bonded IOBs 0 440 0




Busses TOP

dlmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 1.00.a IP


dlmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LMB_Clk I 1 clk_125_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DLMB
dlmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES
Number of Bus Slaves
1
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_EXT_RESET_HIGH
Active High External Reset
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 1 28800 0
Slice LUTs 1 28800 0
LUT Flip Flop pairs used 2 NA NA
fully used LUT-FF pairs 0 2 0
unique control sets 1 NA NA
IOs 211 NA NA
bonded IOBs 0 440 0


ilmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 1.00.a IP


ilmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LMB_Clk I 1 clk_125_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER ILMB
ilmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES
Number of Bus Slaves
1
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_EXT_RESET_HIGH
Active High External Reset
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 1 28800 0
Slice LUTs 1 28800 0
LUT Flip Flop pairs used 2 NA NA
fully used LUT-FF pairs 0 2 0
unique control sets 1 NA NA
IOs 211 NA NA
bonded IOBs 0 440 0


mb_plb   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core Version Documentation
plb_v46 1.04.a IP


mb_plb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 PLB_Clk I 1 clk_125_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DPLB
microblaze_0 MASTER IPLB
xps_intc_0 SLAVE SPLB
mdm_0 SLAVE SPLB
SysACE_CompactFlash SLAVE SPLB
RS232_Uart SLAVE SPLB
my_custom_ip_register_0 SLAVE SPLB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_PLBV46_NUM_MASTERS
Number of PLB Masters
2
C_PLBV46_NUM_SLAVES
Number of PLB Slaves
5
C_PLBV46_MID_WIDTH
PLB Master ID Bus Width
1
C_PLBV46_AWIDTH
PLB Address Bus Width
32
C_PLBV46_DWIDTH
PLB Data Bus Width
32
C_DCR_INTFCE
Include DCR Interface and Error Registers
0
C_BASEADDR
Base Address
0b1111111111
C_HIGHADDR
High Address
0b0000000000
C_DCR_AWIDTH
DCR Address Bus Width
10
 
Name Value
C_DCR_DWIDTH
DCR Data Bus Width
32
C_EXT_RESET_HIGH
External Reset Active High
1
C_IRQ_ACTIVE
IRQ Active State
1
C_NUM_CLK_PLB2OPB_REARB
<qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt>
5
C_ADDR_PIPELINING_TYPE
Enable Address Pipelining Type
1
C_FAMILY
Device Family
virtex5
C_P2P
Optimize PLB for Point-to-point Topology
0
C_ARB_TYPE
Selects the Arbitration Scheme
0
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 152 28800 0
Slice LUTs 342 28800 1
LUT Flip Flop pairs used 362 NA NA
fully used LUT-FF pairs 132 362 36
unique control sets 19 NA NA
IOs 934 NA NA
bonded IOBs 0 440 0




Memorys TOP

lmb_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


lmb_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM ilmb_port ilmb_cntlr
PORTB TARGET XIL_BRAM dlmb_port dlmb_cntlr


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE
Size of BRAM(s) in Bytes
0x20000
C_PORT_DWIDTH
Data Width of Port A and B
32
C_PORT_AWIDTH
Address Width of Port A and B
32
C_NUM_WE
Number of Byte Write Enables
4
C_FAMILY
Device Family
virtex5
Post Synthesis Device Utilization
Resource Type Used Available Percent
LUT Flip Flop pairs used 0 NA NA
fully used LUT-FF pairs 0 0 NA
unique control sets 0 NA NA
IOs 206 NA NA
bonded IOBs 0 440 0
Block RAM/FIFO 32 48 66




Memory Controllers TOP

dlmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 2.10.b IP


dlmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM dlmb_port lmb_bram
SLMB SLAVE LMB dlmb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
LMB BRAM Base Address
0x00000000
C_HIGHADDR
LMB BRAM High Address
0x0001ffff
C_MASK
LMB Address Decode Mask
0x00800000
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 2 28800 0
Slice LUTs 6 28800 0
LUT Flip Flop pairs used 8 NA NA
fully used LUT-FF pairs 0 8 0
unique control sets 1 NA NA
IOs 209 NA NA
bonded IOBs 0 440 0


ilmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 2.10.b IP


ilmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM ilmb_port lmb_bram
SLMB SLAVE LMB ilmb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
LMB BRAM Base Address
0x00000000
C_HIGHADDR
LMB BRAM High Address
0x0001ffff
C_MASK
LMB Address Decode Mask
0x00800000
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 2 28800 0
Slice LUTs 6 28800 0
LUT Flip Flop pairs used 8 NA NA
fully used LUT-FF pairs 0 8 0
unique control sets 1 NA NA
IOs 209 NA NA
bonded IOBs 0 440 0




Peripherals TOP

RS232_Uart   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

IP Specs
Core Version Documentation
xps_uartlite 1.01.a IP


RS232_Uart IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 RX I 1 fpga_0_RS232_Uart_RX_pin
1 TX O 1 fpga_0_RS232_Uart_TX_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 5 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
virtex5
C_SPLB_CLK_FREQ_HZ
Clock Frequency of PLB Slave
125000000
C_BASEADDR
Base Address
0x84000000
C_HIGHADDR
High Address
0x8400ffff
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
 
Name Value
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_BAUDRATE
UART Lite Baud Rate
9600
C_DATA_BITS
Number of Data Bits in a Serial Frame
8
C_USE_PARITY
Use Parity
0
C_ODD_PARITY
Parity Type
0
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 147 28800 0
Slice LUTs 130 28800 0
LUT Flip Flop pairs used 205 NA NA
fully used LUT-FF pairs 72 205 35
unique control sets 33 NA NA
IOs 204 NA NA
bonded IOBs 0 440 0


SysACE_CompactFlash   XPS System ACE Interface Controller(Compact Flash)
Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral

IP Specs
Core Version Documentation
xps_sysace 1.01.a IP


SysACE_CompactFlash IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 SysACE_MPA O 0:6 fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
1 SysACE_CLK I 1 fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
2 SysACE_MPIRQ I 1 fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
3 SysACE_CEN O 1 fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
4 SysACE_OEN O 1 fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
5 SysACE_WEN O 1 fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
6 SysACE_MPD IO 0:15 fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 5 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
Base Address
0x83600000
C_HIGHADDR
High Address
0x8360ffff
C_MEM_WIDTH
Width of System ACE Data Bus
16
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
 
Name Value
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_FAMILY
Device Family
virtex5
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 210 28800 0
Slice LUTs 96 28800 0
LUT Flip Flop pairs used 225 NA NA
fully used LUT-FF pairs 81 225 36
unique control sets 21 NA NA
IOs 262 NA NA
bonded IOBs 0 440 0


my_custom_ip_register_0


IP Specs
Core Version
my_custom_ip_register 1.00.a


my_custom_ip_register_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 IP2INTC_Irpt O 1 my_custom_ip_register_0_IP2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 5 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xccc00000
C_HIGHADDR 0xccc0ffff
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_NUM_MASTERS 2
C_SPLB_MID_WIDTH 1
C_SPLB_NATIVE_DWIDTH 32
 
Name Value
C_SPLB_P2P 0
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_SMALLEST_MASTER 32
C_SPLB_CLK_PERIOD_PS 8000
C_INCLUDE_DPHASE_TIMER 1
C_FAMILY virtex5
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 132 28800 0
Slice LUTs 139 28800 0
LUT Flip Flop pairs used 202 NA NA
fully used LUT-FF pairs 69 202 34
unique control sets 19 NA NA
IOs 202 NA NA
bonded IOBs 0 440 0


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 2.00.a IP


proc_sys_reset_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Slowest_sync_clk I 1 clk_125_0000MHz
1 Ext_Reset_In I 1 sys_rst_s
2 MB_Debug_Sys_Rst I 1 Debug_SYS_Rst
3 Dcm_locked I 1 Dcm_all_locked
4 MB_Reset O 1 mb_reset
5 Bus_Struct_Reset O 1 sys_bus_reset


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SUBFAMILY
Device Subfamily
lx
C_EXT_RST_WIDTH
Number of Clocks Before Input Change is Recognized On The External Reset Input
4
C_AUX_RST_WIDTH
Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input
4
C_EXT_RESET_HIGH
External Reset Active High
0
C_AUX_RESET_HIGH
Auxiliary Reset Active High
1
C_NUM_BUS_RST
Number of Bus Structure Reset Registered Outputs
1
C_NUM_PERP_RST
Number of Peripheral Reset Registered Outputs
1
C_FAMILY
Device Family
virtex5
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice Registers 67 28800 0
Slice LUTs 51 28800 0
LUT Flip Flop pairs used 72 NA NA
fully used LUT-FF pairs 46 72 63
unique control sets 29 NA NA
IOs 20 NA NA
bonded IOBs 0 440 0




IP TOP

clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 3.02.a IP


clock_generator_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 CLKIN I 1 dcm_clk_s
1 CLKOUT0 O 1 clk_125_0000MHz
2 RST I 1 sys_rst_s
3 LOCKED O 1 Dcm_all_locked


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Family
virtex5
C_SPEEDGRADE
Speed Grade
-1
C_EXT_RESET_HIGH
External Reset
0
C_CLK_GEN
C_CLK_GEN
update
C_CLKOUT0_MODULE
C_CLKOUT0_MODULE
NONE
C_CLKOUT0_PORT
C_CLKOUT0_PORT
NONE
C_CLKOUT1_MODULE
C_CLKOUT1_MODULE
NONE
C_CLKOUT1_PORT
C_CLKOUT1_PORT
NONE
C_CLKOUT2_MODULE
C_CLKOUT2_MODULE
NONE
C_CLKOUT2_PORT
C_CLKOUT2_PORT
NONE
C_CLKOUT3_MODULE
C_CLKOUT3_MODULE
NONE
C_CLKOUT3_PORT
C_CLKOUT3_PORT
NONE
C_CLKOUT4_MODULE
C_CLKOUT4_MODULE
NONE
C_CLKOUT4_PORT
C_CLKOUT4_PORT
NONE
C_CLKOUT5_MODULE
C_CLKOUT5_MODULE
NONE
C_CLKOUT5_PORT
C_CLKOUT5_PORT
NONE
C_CLKOUT6_MODULE
C_CLKOUT6_MODULE
NONE
C_CLKOUT6_PORT
C_CLKOUT6_PORT
NONE
C_CLKOUT7_MODULE
C_CLKOUT7_MODULE
NONE
C_CLKOUT7_PORT
C_CLKOUT7_PORT
NONE
C_CLKOUT8_MODULE
C_CLKOUT8_MODULE
NONE
C_CLKOUT8_PORT
C_CLKOUT8_PORT
NONE
C_CLKOUT9_MODULE
C_CLKOUT9_MODULE
NONE
C_CLKOUT9_PORT
C_CLKOUT9_PORT
NONE
C_CLKOUT10_MODULE
C_CLKOUT10_MODULE
NONE
C_CLKOUT10_PORT
C_CLKOUT10_PORT
NONE
C_CLKOUT11_MODULE
C_CLKOUT11_MODULE
NONE
C_CLKOUT11_PORT
C_CLKOUT11_PORT
NONE
C_CLKOUT12_MODULE
C_CLKOUT12_MODULE
NONE
C_CLKOUT12_PORT
C_CLKOUT12_PORT
NONE
C_CLKOUT13_MODULE
C_CLKOUT13_MODULE
NONE
C_CLKOUT13_PORT
C_CLKOUT13_PORT
NONE
C_CLKOUT14_MODULE
C_CLKOUT14_MODULE
NONE
C_CLKOUT14_PORT
C_CLKOUT14_PORT
NONE
C_CLKOUT15_MODULE
C_CLKOUT15_MODULE
NONE
C_CLKOUT15_PORT
C_CLKOUT15_PORT
NONE
C_CLKFBOUT_MODULE
C_CLKFBOUT_MODULE
NONE
C_CLKFBOUT_PORT
C_CLKFBOUT_PORT
NONE
C_PSDONE_MODULE
C_PSDONE_MODULE
NONE
C_PLL0_DIVCLK_DIVIDE
C_PLL0_DIVCLK_DIVIDE
1
C_PLL0_CLKFBOUT_MULT
C_PLL0_CLKFBOUT_MULT
1
C_PLL0_CLKFBOUT_PHASE
C_PLL0_CLKFBOUT_PHASE
0.000000
C_PLL0_CLKIN1_PERIOD
C_PLL0_CLKIN1_PERIOD
0.000000
C_PLL0_CLKOUT0_DIVIDE
C_PLL0_CLKOUT0_DIVIDE
1
C_PLL0_CLKOUT0_DUTY_CYCLE
C_PLL0_CLKOUT0_DUTY_CYCLE
0.500000
C_PLL0_CLKOUT0_PHASE
C_PLL0_CLKOUT0_PHASE
0.000000
C_PLL0_CLKOUT1_DIVIDE
C_PLL0_CLKOUT1_DIVIDE
1
C_PLL0_CLKOUT1_DUTY_CYCLE
C_PLL0_CLKOUT1_DUTY_CYCLE
0.500000
C_PLL0_CLKOUT1_PHASE
C_PLL0_CLKOUT1_PHASE
0.000000
C_PLL0_CLKOUT2_DIVIDE
C_PLL0_CLKOUT2_DIVIDE
1
C_PLL0_CLKOUT2_DUTY_CYCLE
C_PLL0_CLKOUT2_DUTY_CYCLE
0.500000
C_PLL0_CLKOUT2_PHASE
C_PLL0_CLKOUT2_PHASE
0.000000
C_PLL0_CLKOUT3_DIVIDE
C_PLL0_CLKOUT3_DIVIDE
1
C_PLL0_CLKOUT3_DUTY_CYCLE
C_PLL0_CLKOUT3_DUTY_CYCLE
0.500000
C_PLL0_CLKOUT3_PHASE
C_PLL0_CLKOUT3_PHASE
0.000000
C_PLL0_CLKOUT4_DIVIDE
C_PLL0_CLKOUT4_DIVIDE
1
C_PLL0_CLKOUT4_DUTY_CYCLE
C_PLL0_CLKOUT4_DUTY_CYCLE
0.500000
C_PLL0_CLKOUT4_PHASE
C_PLL0_CLKOUT4_PHASE
0.000000
C_PLL0_CLKOUT5_DIVIDE
C_PLL0_CLKOUT5_DIVIDE
1
C_PLL0_CLKOUT5_DUTY_CYCLE
C_PLL0_CLKOUT5_DUTY_CYCLE
0.500000
C_PLL0_CLKOUT5_PHASE
C_PLL0_CLKOUT5_PHASE
0.000000
C_PLL0_BANDWIDTH
C_PLL0_BANDWIDTH
OPTIMIZED
C_PLL0_COMPENSATION
C_PLL0_COMPENSATION
SYSTEM_SYNCHRONOUS
C_PLL0_REF_JITTER
C_PLL0_REF_JITTER
0.100000
C_PLL0_RESET_ON_LOSS_OF_LOCK
C_PLL0_RESET_ON_LOSS_OF_LOCK
false
C_PLL0_RST_DEASSERT_CLK
C_PLL0_RST_DEASSERT_CLK
CLKIN1
C_PLL0_EXT_RESET_HIGH
C_PLL0_EXT_RESET_HIGH
1
C_PLL0_FAMILY
C_PLL0_FAMILY
virtex5
C_PLL0_CLKOUT0_DESKEW_ADJUST
C_PLL0_CLKOUT0_DESKEW_ADJUST
NONE
C_PLL0_CLKOUT1_DESKEW_ADJUST
C_PLL0_CLKOUT1_DESKEW_ADJUST
NONE
C_PLL0_CLKOUT2_DESKEW_ADJUST
C_PLL0_CLKOUT2_DESKEW_ADJUST
NONE
C_PLL0_CLKOUT3_DESKEW_ADJUST
C_PLL0_CLKOUT3_DESKEW_ADJUST
NONE
C_PLL0_CLKOUT4_DESKEW_ADJUST
C_PLL0_CLKOUT4_DESKEW_ADJUST
NONE
C_PLL0_CLKOUT5_DESKEW_ADJUST
C_PLL0_CLKOUT5_DESKEW_ADJUST
NONE
C_PLL0_CLKFBOUT_DESKEW_ADJUST
C_PLL0_CLKFBOUT_DESKEW_ADJUST
NONE
C_PLL0_CLKIN1_BUF
C_PLL0_CLKIN1_BUF
false
C_PLL0_CLKFBOUT_BUF
C_PLL0_CLKFBOUT_BUF
false
C_PLL0_CLKOUT0_BUF
C_PLL0_CLKOUT0_BUF
false
C_PLL0_CLKOUT1_BUF
C_PLL0_CLKOUT1_BUF
false
C_PLL0_CLKOUT2_BUF
C_PLL0_CLKOUT2_BUF
false
C_PLL0_CLKOUT3_BUF
C_PLL0_CLKOUT3_BUF
false
C_PLL0_CLKOUT4_BUF
C_PLL0_CLKOUT4_BUF
false
C_PLL0_CLKOUT5_BUF
C_PLL0_CLKOUT5_BUF
false
C_PLL0_CLKIN1_MODULE
C_PLL0_CLKIN1_MODULE
NONE
C_PLL0_CLKIN1_PORT
C_PLL0_CLKIN1_PORT
NONE
C_PLL0_CLKFBIN_MODULE
C_PLL0_CLKFBIN_MODULE
NONE
C_PLL0_CLKFBIN_PORT
C_PLL0_CLKFBIN_PORT
NONE
C_PLL0_RST_MODULE
C_PLL0_RST_MODULE
NONE
C_PLL1_DIVCLK_DIVIDE
C_PLL1_DIVCLK_DIVIDE
1
C_PLL1_CLKFBOUT_MULT
C_PLL1_CLKFBOUT_MULT
1
C_PLL1_CLKFBOUT_PHASE
C_PLL1_CLKFBOUT_PHASE
0.000000
C_PLL1_CLKIN1_PERIOD
C_PLL1_CLKIN1_PERIOD
0.000000
C_PLL1_CLKOUT0_DIVIDE
C_PLL1_CLKOUT0_DIVIDE
1
C_PLL1_CLKOUT0_DUTY_CYCLE
C_PLL1_CLKOUT0_DUTY_CYCLE
0.500000
C_PLL1_CLKOUT0_PHASE
C_PLL1_CLKOUT0_PHASE
0.000000
C_PLL1_CLKOUT1_DIVIDE
C_PLL1_CLKOUT1_DIVIDE
1
C_PLL1_CLKOUT1_DUTY_CYCLE
C_PLL1_CLKOUT1_DUTY_CYCLE
0.500000
C_PLL1_CLKOUT1_PHASE
C_PLL1_CLKOUT1_PHASE
0.000000
C_PLL1_CLKOUT2_DIVIDE
C_PLL1_CLKOUT2_DIVIDE
1
C_PLL1_CLKOUT2_DUTY_CYCLE
C_PLL1_CLKOUT2_DUTY_CYCLE
0.500000
C_PLL1_CLKOUT2_PHASE
C_PLL1_CLKOUT2_PHASE
0.000000
C_PLL1_CLKOUT3_DIVIDE
C_PLL1_CLKOUT3_DIVIDE
1
C_PLL1_CLKOUT3_DUTY_CYCLE
C_PLL1_CLKOUT3_DUTY_CYCLE
0.500000
C_PLL1_CLKOUT3_PHASE
C_PLL1_CLKOUT3_PHASE
0.000000
C_PLL1_CLKOUT4_DIVIDE
C_PLL1_CLKOUT4_DIVIDE
1
C_PLL1_CLKOUT4_DUTY_CYCLE
C_PLL1_CLKOUT4_DUTY_CYCLE
0.500000
C_PLL1_CLKOUT4_PHASE
C_PLL1_CLKOUT4_PHASE
0.000000
C_PLL1_CLKOUT5_DIVIDE
C_PLL1_CLKOUT5_DIVIDE
1
C_PLL1_CLKOUT5_DUTY_CYCLE
C_PLL1_CLKOUT5_DUTY_CYCLE
0.500000
C_PLL1_CLKOUT5_PHASE
C_PLL1_CLKOUT5_PHASE
0.000000
C_PLL1_BANDWIDTH
C_PLL1_BANDWIDTH
OPTIMIZED
C_PLL1_COMPENSATION
C_PLL1_COMPENSATION
SYSTEM_SYNCHRONOUS
C_PLL1_REF_JITTER
C_PLL1_REF_JITTER
0.100000
C_PLL1_RESET_ON_LOSS_OF_LOCK
C_PLL1_RESET_ON_LOSS_OF_LOCK
false
C_PLL1_RST_DEASSERT_CLK
C_PLL1_RST_DEASSERT_CLK
CLKIN1
C_PLL1_EXT_RESET_HIGH
C_PLL1_EXT_RESET_HIGH
1
C_PLL1_FAMILY
C_PLL1_FAMILY
virtex5
C_PLL1_CLKOUT0_DESKEW_ADJUST
C_PLL1_CLKOUT0_DESKEW_ADJUST
NONE
C_PLL1_CLKOUT1_DESKEW_ADJUST
C_PLL1_CLKOUT1_DESKEW_ADJUST
NONE
C_PLL1_CLKOUT2_DESKEW_ADJUST
C_PLL1_CLKOUT2_DESKEW_ADJUST
NONE
C_PLL1_CLKOUT3_DESKEW_ADJUST
C_PLL1_CLKOUT3_DESKEW_ADJUST
NONE
C_PLL1_CLKOUT4_DESKEW_ADJUST
C_PLL1_CLKOUT4_DESKEW_ADJUST
NONE
C_PLL1_CLKOUT5_DESKEW_ADJUST
C_PLL1_CLKOUT5_DESKEW_ADJUST
NONE
C_PLL1_CLKFBOUT_DESKEW_ADJUST
C_PLL1_CLKFBOUT_DESKEW_ADJUST
NONE
C_PLL1_CLKIN1_BUF
C_PLL1_CLKIN1_BUF
false
C_PLL1_CLKFBOUT_BUF
C_PLL1_CLKFBOUT_BUF
false
C_PLL1_CLKOUT0_BUF
C_PLL1_CLKOUT0_BUF
false
C_PLL1_CLKOUT1_BUF
C_PLL1_CLKOUT1_BUF
false
C_PLL1_CLKOUT2_BUF
C_PLL1_CLKOUT2_BUF
false
C_PLL1_CLKOUT3_BUF
C_PLL1_CLKOUT3_BUF
false
C_PLL1_CLKOUT4_BUF
C_PLL1_CLKOUT4_BUF
false
C_PLL1_CLKOUT5_BUF
C_PLL1_CLKOUT5_BUF
false
C_PLL1_CLKIN1_MODULE
C_PLL1_CLKIN1_MODULE
NONE
C_PLL1_CLKIN1_PORT
C_PLL1_CLKIN1_PORT
NONE
C_PLL1_CLKFBIN_MODULE
C_PLL1_CLKFBIN_MODULE
NONE
C_PLL1_CLKFBIN_PORT
C_PLL1_CLKFBIN_PORT
NONE
C_PLL1_RST_MODULE
C_PLL1_RST_MODULE
NONE
C_DCM0_DFS_FREQUENCY_MODE
C_DCM0_DFS_FREQUENCY_MODE
LOW
C_DCM0_DLL_FREQUENCY_MODE
C_DCM0_DLL_FREQUENCY_MODE
LOW
C_DCM0_DUTY_CYCLE_CORRECTION
C_DCM0_DUTY_CYCLE_CORRECTION
true
C_DCM0_CLKIN_DIVIDE_BY_2
C_DCM0_CLKIN_DIVIDE_BY_2
false
C_DCM0_CLK_FEEDBACK
C_DCM0_CLK_FEEDBACK
1X
C_DCM0_CLKOUT_PHASE_SHIFT
C_DCM0_CLKOUT_PHASE_SHIFT
NONE
C_DCM0_DSS_MODE
C_DCM0_DSS_MODE
NONE
C_DCM0_STARTUP_WAIT
C_DCM0_STARTUP_WAIT
false
C_DCM0_PHASE_SHIFT
C_DCM0_PHASE_SHIFT
0
C_DCM0_CLKFX_MULTIPLY
C_DCM0_CLKFX_MULTIPLY
4
C_DCM0_CLKFX_DIVIDE
C_DCM0_CLKFX_DIVIDE
1
C_DCM0_CLKDV_DIVIDE
C_DCM0_CLKDV_DIVIDE
2.000000
C_DCM0_CLKIN_PERIOD
C_DCM0_CLKIN_PERIOD
0.000000
C_DCM0_DESKEW_ADJUST
C_DCM0_DESKEW_ADJUST
SYSTEM_SYNCHRONOUS
C_DCM0_CLKIN_BUF
C_DCM0_CLKIN_BUF
false
C_DCM0_CLKFB_BUF
C_DCM0_CLKFB_BUF
false
C_DCM0_CLK0_BUF
C_DCM0_CLK0_BUF
false
C_DCM0_CLK90_BUF
C_DCM0_CLK90_BUF
false
C_DCM0_CLK180_BUF
C_DCM0_CLK180_BUF
false
C_DCM0_CLK270_BUF
C_DCM0_CLK270_BUF
false
C_DCM0_CLKDV_BUF
C_DCM0_CLKDV_BUF
false
C_DCM0_CLKDV180_BUF
C_DCM0_CLKDV180_BUF
false
C_DCM0_CLK2X_BUF
C_DCM0_CLK2X_BUF
false
C_DCM0_CLK2X180_BUF
C_DCM0_CLK2X180_BUF
false
C_DCM0_CLKFX_BUF
C_DCM0_CLKFX_BUF
false
C_DCM0_CLKFX180_BUF
C_DCM0_CLKFX180_BUF
false
C_DCM0_EXT_RESET_HIGH
C_DCM0_EXT_RESET_HIGH
1
C_DCM0_FAMILY
C_DCM0_FAMILY
virtex5
C_DCM0_CLKIN_MODULE
C_DCM0_CLKIN_MODULE
NONE
C_DCM0_CLKIN_PORT
C_DCM0_CLKIN_PORT
NONE
C_DCM0_CLKFB_MODULE
C_DCM0_CLKFB_MODULE
NONE
C_DCM0_CLKFB_PORT
C_DCM0_CLKFB_PORT
NONE
C_DCM0_RST_MODULE
C_DCM0_RST_MODULE
NONE
C_DCM1_DFS_FREQUENCY_MODE
C_DCM1_DFS_FREQUENCY_MODE
LOW
C_DCM1_DLL_FREQUENCY_MODE
C_DCM1_DLL_FREQUENCY_MODE
LOW
C_DCM1_DUTY_CYCLE_CORRECTION
C_DCM1_DUTY_CYCLE_CORRECTION
true
C_DCM1_CLKIN_DIVIDE_BY_2
C_DCM1_CLKIN_DIVIDE_BY_2
false
C_DCM1_CLK_FEEDBACK
C_DCM1_CLK_FEEDBACK
1X
C_DCM1_CLKOUT_PHASE_SHIFT
C_DCM1_CLKOUT_PHASE_SHIFT
NONE
C_DCM1_DSS_MODE
C_DCM1_DSS_MODE
NONE
C_DCM1_STARTUP_WAIT
C_DCM1_STARTUP_WAIT
false
C_DCM1_PHASE_SHIFT
C_DCM1_PHASE_SHIFT
0
C_DCM1_CLKFX_MULTIPLY
C_DCM1_CLKFX_MULTIPLY
4
C_DCM1_CLKFX_DIVIDE
C_DCM1_CLKFX_DIVIDE
1
C_DCM1_CLKDV_DIVIDE
C_DCM1_CLKDV_DIVIDE
2.000000
C_DCM1_CLKIN_PERIOD
C_DCM1_CLKIN_PERIOD
0.000000
C_DCM1_DESKEW_ADJUST
C_DCM1_DESKEW_ADJUST
SYSTEM_SYNCHRONOUS
C_DCM1_CLKIN_BUF
C_DCM1_CLKIN_BUF
false
C_DCM1_CLKFB_BUF
C_DCM1_CLKFB_BUF
false
C_DCM1_CLK0_BUF
C_DCM1_CLK0_BUF
false
C_DCM1_CLK90_BUF
C_DCM1_CLK90_BUF
false
C_DCM1_CLK180_BUF
C_DCM1_CLK180_BUF
false
C_DCM1_CLK270_BUF
C_DCM1_CLK270_BUF
false
C_DCM1_CLKDV_BUF
C_DCM1_CLKDV_BUF
false
C_DCM1_CLKDV180_BUF
C_DCM1_CLKDV180_BUF
false
C_DCM1_CLK2X_BUF
C_DCM1_CLK2X_BUF
false
C_DCM1_CLK2X180_BUF
C_DCM1_CLK2X180_BUF
false
C_DCM1_CLKFX_BUF
C_DCM1_CLKFX_BUF
false
C_DCM1_CLKFX180_BUF
C_DCM1_CLKFX180_BUF
false
C_DCM1_EXT_RESET_HIGH
C_DCM1_EXT_RESET_HIGH
1
C_DCM1_FAMILY
C_DCM1_FAMILY
virtex5
C_DCM1_CLKIN_MODULE
C_DCM1_CLKIN_MODULE
NONE
C_DCM1_CLKIN_PORT
C_DCM1_CLKIN_PORT
NONE
C_DCM1_CLKFB_MODULE
C_DCM1_CLKFB_MODULE
NONE
C_DCM1_CLKFB_PORT
C_DCM1_CLKFB_PORT
NONE
C_DCM1_RST_MODULE
C_DCM1_RST_MODULE
NONE
C_DCM2_DFS_FREQUENCY_MODE
C_DCM2_DFS_FREQUENCY_MODE
LOW
C_DCM2_DLL_FREQUENCY_MODE
C_DCM2_DLL_FREQUENCY_MODE
LOW
C_DCM2_DUTY_CYCLE_CORRECTION
C_DCM2_DUTY_CYCLE_CORRECTION
true
C_DCM2_CLKIN_DIVIDE_BY_2
C_DCM2_CLKIN_DIVIDE_BY_2
false
C_DCM2_CLK_FEEDBACK
C_DCM2_CLK_FEEDBACK
1X
C_DCM2_CLKOUT_PHASE_SHIFT
C_DCM2_CLKOUT_PHASE_SHIFT
NONE
C_DCM2_DSS_MODE
C_DCM2_DSS_MODE
NONE
C_DCM2_STARTUP_WAIT
C_DCM2_STARTUP_WAIT
false
C_DCM2_PHASE_SHIFT
C_DCM2_PHASE_SHIFT
0
C_DCM2_CLKFX_MULTIPLY
C_DCM2_CLKFX_MULTIPLY
4
C_DCM2_CLKFX_DIVIDE
C_DCM2_CLKFX_DIVIDE
1
C_DCM2_CLKDV_DIVIDE
C_DCM2_CLKDV_DIVIDE
2.000000
C_DCM2_CLKIN_PERIOD
C_DCM2_CLKIN_PERIOD
0.000000
C_DCM2_DESKEW_ADJUST
C_DCM2_DESKEW_ADJUST
SYSTEM_SYNCHRONOUS
C_DCM2_CLKIN_BUF
C_DCM2_CLKIN_BUF
false
C_DCM2_CLKFB_BUF
C_DCM2_CLKFB_BUF
false
C_DCM2_CLK0_BUF
C_DCM2_CLK0_BUF
false
C_DCM2_CLK90_BUF
C_DCM2_CLK90_BUF
false
C_DCM2_CLK180_BUF
C_DCM2_CLK180_BUF
false
C_DCM2_CLK270_BUF
C_DCM2_CLK270_BUF
false
C_DCM2_CLKDV_BUF
C_DCM2_CLKDV_BUF
false
C_DCM2_CLKDV180_BUF
C_DCM2_CLKDV180_BUF
false
C_DCM2_CLK2X_BUF
C_DCM2_CLK2X_BUF
false
C_DCM2_CLK2X180_BUF
C_DCM2_CLK2X180_BUF
false
C_DCM2_CLKFX_BUF
C_DCM2_CLKFX_BUF
false
C_DCM2_CLKFX180_BUF
C_DCM2_CLKFX180_BUF
false
C_DCM2_EXT_RESET_HIGH
C_DCM2_EXT_RESET_HIGH
1
C_DCM2_FAMILY
C_DCM2_FAMILY
virtex5
C_DCM2_CLKIN_MODULE
C_DCM2_CLKIN_MODULE
NONE
C_DCM2_CLKIN_PORT
C_DCM2_CLKIN_PORT
NONE
C_DCM2_CLKFB_MODULE
C_DCM2_CLKFB_MODULE
NONE
C_DCM2_CLKFB_PORT
C_DCM2_CLKFB_PORT
NONE
C_DCM2_RST_MODULE
C_DCM2_RST_MODULE
NONE
C_DCM3_DFS_FREQUENCY_MODE
C_DCM3_DFS_FREQUENCY_MODE
LOW
C_DCM3_DLL_FREQUENCY_MODE
C_DCM3_DLL_FREQUENCY_MODE
LOW
C_DCM3_DUTY_CYCLE_CORRECTION
C_DCM3_DUTY_CYCLE_CORRECTION
true
C_DCM3_CLKIN_DIVIDE_BY_2
C_DCM3_CLKIN_DIVIDE_BY_2
false
C_DCM3_CLK_FEEDBACK
C_DCM3_CLK_FEEDBACK
1X
C_DCM3_CLKOUT_PHASE_SHIFT
C_DCM3_CLKOUT_PHASE_SHIFT
NONE
C_DCM3_DSS_MODE
C_DCM3_DSS_MODE
NONE
C_DCM3_STARTUP_WAIT
C_DCM3_STARTUP_WAIT
false
C_DCM3_PHASE_SHIFT
C_DCM3_PHASE_SHIFT
0
C_DCM3_CLKFX_MULTIPLY
C_DCM3_CLKFX_MULTIPLY
4
C_DCM3_CLKFX_DIVIDE
C_DCM3_CLKFX_DIVIDE
1
C_DCM3_CLKDV_DIVIDE
C_DCM3_CLKDV_DIVIDE
2.000000
C_DCM3_CLKIN_PERIOD
C_DCM3_CLKIN_PERIOD
0.000000
C_DCM3_DESKEW_ADJUST
C_DCM3_DESKEW_ADJUST
SYSTEM_SYNCHRONOUS
C_DCM3_CLKIN_BUF
C_DCM3_CLKIN_BUF
false
C_DCM3_CLKFB_BUF
C_DCM3_CLKFB_BUF
false
C_DCM3_CLK0_BUF
C_DCM3_CLK0_BUF
false
C_DCM3_CLK90_BUF
C_DCM3_CLK90_BUF
false
C_DCM3_CLK180_BUF
C_DCM3_CLK180_BUF
false
C_DCM3_CLK270_BUF
C_DCM3_CLK270_BUF
false
C_DCM3_CLKDV_BUF
C_DCM3_CLKDV_BUF
false
C_DCM3_CLKDV180_BUF
C_DCM3_CLKDV180_BUF
false
C_DCM3_CLK2X_BUF
C_DCM3_CLK2X_BUF
false
C_DCM3_CLK2X180_BUF
C_DCM3_CLK2X180_BUF
false
C_DCM3_CLKFX_BUF
C_DCM3_CLKFX_BUF
false
C_DCM3_CLKFX180_BUF
C_DCM3_CLKFX180_BUF
false
C_DCM3_EXT_RESET_HIGH
C_DCM3_EXT_RESET_HIGH
1
C_DCM3_FAMILY
C_DCM3_FAMILY
virtex5
C_DCM3_CLKIN_MODULE
C_DCM3_CLKIN_MODULE
NONE
C_DCM3_CLKIN_PORT
C_DCM3_CLKIN_PORT
NONE
C_DCM3_CLKFB_MODULE
C_DCM3_CLKFB_MODULE
NONE
C_DCM3_CLKFB_PORT
C_DCM3_CLKFB_PORT
NONE
C_DCM3_RST_MODULE
C_DCM3_RST_MODULE
NONE
C_MMCM0_BANDWIDTH
C_MMCM0_BANDWIDTH
OPTIMIZED
C_MMCM0_CLKFBOUT_MULT_F
C_MMCM0_CLKFBOUT_MULT_F
1.000000
C_MMCM0_CLKFBOUT_PHASE
C_MMCM0_CLKFBOUT_PHASE
0.000000
C_MMCM0_CLKFBOUT_USE_FINE_PS
C_MMCM0_CLKFBOUT_USE_FINE_PS
false
C_MMCM0_CLKIN1_PERIOD
C_MMCM0_CLKIN1_PERIOD
0.000000
C_MMCM0_CLKOUT0_DIVIDE_F
C_MMCM0_CLKOUT0_DIVIDE_F
1.000000
C_MMCM0_CLKOUT0_DUTY_CYCLE
C_MMCM0_CLKOUT0_DUTY_CYCLE
0.500000
C_MMCM0_CLKOUT0_PHASE
C_MMCM0_CLKOUT0_PHASE
0.000000
C_MMCM0_CLKOUT1_DIVIDE
C_MMCM0_CLKOUT1_DIVIDE
1
C_MMCM0_CLKOUT1_DUTY_CYCLE
C_MMCM0_CLKOUT1_DUTY_CYCLE
0.500000
C_MMCM0_CLKOUT1_PHASE
C_MMCM0_CLKOUT1_PHASE
0.000000
C_MMCM0_CLKOUT2_DIVIDE
C_MMCM0_CLKOUT2_DIVIDE
1
C_MMCM0_CLKOUT2_DUTY_CYCLE
C_MMCM0_CLKOUT2_DUTY_CYCLE
0.500000
C_MMCM0_CLKOUT2_PHASE
C_MMCM0_CLKOUT2_PHASE
0.000000
C_MMCM0_CLKOUT3_DIVIDE
C_MMCM0_CLKOUT3_DIVIDE
1
C_MMCM0_CLKOUT3_DUTY_CYCLE
C_MMCM0_CLKOUT3_DUTY_CYCLE
0.500000
C_MMCM0_CLKOUT3_PHASE
C_MMCM0_CLKOUT3_PHASE
0.000000
C_MMCM0_CLKOUT4_DIVIDE
C_MMCM0_CLKOUT4_DIVIDE
1
C_MMCM0_CLKOUT4_DUTY_CYCLE
C_MMCM0_CLKOUT4_DUTY_CYCLE
0.500000
C_MMCM0_CLKOUT4_PHASE
C_MMCM0_CLKOUT4_PHASE
0.000000
 
Name Value
C_MMCM0_CLKOUT4_CASCADE
C_MMCM0_CLKOUT4_CASCADE
false
C_MMCM0_CLKOUT5_DIVIDE
C_MMCM0_CLKOUT5_DIVIDE
1
C_MMCM0_CLKOUT5_DUTY_CYCLE
C_MMCM0_CLKOUT5_DUTY_CYCLE
0.500000
C_MMCM0_CLKOUT5_PHASE
C_MMCM0_CLKOUT5_PHASE
0.000000
C_MMCM0_CLKOUT6_DIVIDE
C_MMCM0_CLKOUT6_DIVIDE
1
C_MMCM0_CLKOUT6_DUTY_CYCLE
C_MMCM0_CLKOUT6_DUTY_CYCLE
0.500000
C_MMCM0_CLKOUT6_PHASE
C_MMCM0_CLKOUT6_PHASE
0.000000
C_MMCM0_CLKOUT0_USE_FINE_PS
C_MMCM0_CLKOUT0_USE_FINE_PS
false
C_MMCM0_CLKOUT1_USE_FINE_PS
C_MMCM0_CLKOUT1_USE_FINE_PS
false
C_MMCM0_CLKOUT2_USE_FINE_PS
C_MMCM0_CLKOUT2_USE_FINE_PS
false
C_MMCM0_CLKOUT3_USE_FINE_PS
C_MMCM0_CLKOUT3_USE_FINE_PS
false
C_MMCM0_CLKOUT4_USE_FINE_PS
C_MMCM0_CLKOUT4_USE_FINE_PS
false
C_MMCM0_CLKOUT5_USE_FINE_PS
C_MMCM0_CLKOUT5_USE_FINE_PS
false
C_MMCM0_CLKOUT6_USE_FINE_PS
C_MMCM0_CLKOUT6_USE_FINE_PS
false
C_MMCM0_COMPENSATION
C_MMCM0_COMPENSATION
ZHOLD
C_MMCM0_DIVCLK_DIVIDE
C_MMCM0_DIVCLK_DIVIDE
1
C_MMCM0_REF_JITTER1
C_MMCM0_REF_JITTER1
0.010000
C_MMCM0_CLKIN1_BUF
C_MMCM0_CLKIN1_BUF
false
C_MMCM0_CLKFBOUT_BUF
C_MMCM0_CLKFBOUT_BUF
false
C_MMCM0_CLOCK_HOLD
C_MMCM0_CLOCK_HOLD
false
C_MMCM0_STARTUP_WAIT
C_MMCM0_STARTUP_WAIT
false
C_MMCM0_EXT_RESET_HIGH
C_MMCM0_EXT_RESET_HIGH
1
C_MMCM0_FAMILY
C_MMCM0_FAMILY
virtex6
C_MMCM0_CLKOUT0_BUF
C_MMCM0_CLKOUT0_BUF
false
C_MMCM0_CLKOUT1_BUF
C_MMCM0_CLKOUT1_BUF
false
C_MMCM0_CLKOUT2_BUF
C_MMCM0_CLKOUT2_BUF
false
C_MMCM0_CLKOUT3_BUF
C_MMCM0_CLKOUT3_BUF
false
C_MMCM0_CLKOUT4_BUF
C_MMCM0_CLKOUT4_BUF
false
C_MMCM0_CLKOUT5_BUF
C_MMCM0_CLKOUT5_BUF
false
C_MMCM0_CLKOUT6_BUF
C_MMCM0_CLKOUT6_BUF
false
C_MMCM0_CLKIN1_MODULE
C_MMCM0_CLKIN1_MODULE
NONE
C_MMCM0_CLKIN1_PORT
C_MMCM0_CLKIN1_PORT
NONE
C_MMCM0_CLKFBIN_MODULE
C_MMCM0_CLKFBIN_MODULE
NONE
C_MMCM0_CLKFBIN_PORT
C_MMCM0_CLKFBIN_PORT
NONE
C_MMCM0_RST_MODULE
C_MMCM0_RST_MODULE
NONE
C_MMCM1_BANDWIDTH
C_MMCM1_BANDWIDTH
OPTIMIZED
C_MMCM1_CLKFBOUT_MULT_F
C_MMCM1_CLKFBOUT_MULT_F
1.000000
C_MMCM1_CLKFBOUT_PHASE
C_MMCM1_CLKFBOUT_PHASE
0.000000
C_MMCM1_CLKFBOUT_USE_FINE_PS
C_MMCM1_CLKFBOUT_USE_FINE_PS
false
C_MMCM1_CLKIN1_PERIOD
C_MMCM1_CLKIN1_PERIOD
0.000000
C_MMCM1_CLKOUT0_DIVIDE_F
C_MMCM1_CLKOUT0_DIVIDE_F
1.000000
C_MMCM1_CLKOUT0_DUTY_CYCLE
C_MMCM1_CLKOUT0_DUTY_CYCLE
0.500000
C_MMCM1_CLKOUT0_PHASE
C_MMCM1_CLKOUT0_PHASE
0.000000
C_MMCM1_CLKOUT1_DIVIDE
C_MMCM1_CLKOUT1_DIVIDE
1
C_MMCM1_CLKOUT1_DUTY_CYCLE
C_MMCM1_CLKOUT1_DUTY_CYCLE
0.500000
C_MMCM1_CLKOUT1_PHASE
C_MMCM1_CLKOUT1_PHASE
0.000000
C_MMCM1_CLKOUT2_DIVIDE
C_MMCM1_CLKOUT2_DIVIDE
1
C_MMCM1_CLKOUT2_DUTY_CYCLE
C_MMCM1_CLKOUT2_DUTY_CYCLE
0.500000
C_MMCM1_CLKOUT2_PHASE
C_MMCM1_CLKOUT2_PHASE
0.000000
C_MMCM1_CLKOUT3_DIVIDE
C_MMCM1_CLKOUT3_DIVIDE
1
C_MMCM1_CLKOUT3_DUTY_CYCLE
C_MMCM1_CLKOUT3_DUTY_CYCLE
0.500000
C_MMCM1_CLKOUT3_PHASE
C_MMCM1_CLKOUT3_PHASE
0.000000
C_MMCM1_CLKOUT4_DIVIDE
C_MMCM1_CLKOUT4_DIVIDE
1
C_MMCM1_CLKOUT4_DUTY_CYCLE
C_MMCM1_CLKOUT4_DUTY_CYCLE
0.500000
C_MMCM1_CLKOUT4_PHASE
C_MMCM1_CLKOUT4_PHASE
0.000000
C_MMCM1_CLKOUT4_CASCADE
C_MMCM1_CLKOUT4_CASCADE
false
C_MMCM1_CLKOUT5_DIVIDE
C_MMCM1_CLKOUT5_DIVIDE
1
C_MMCM1_CLKOUT5_DUTY_CYCLE
C_MMCM1_CLKOUT5_DUTY_CYCLE
0.500000
C_MMCM1_CLKOUT5_PHASE
C_MMCM1_CLKOUT5_PHASE
0.000000
C_MMCM1_CLKOUT6_DIVIDE
C_MMCM1_CLKOUT6_DIVIDE
1
C_MMCM1_CLKOUT6_DUTY_CYCLE
C_MMCM1_CLKOUT6_DUTY_CYCLE
0.500000
C_MMCM1_CLKOUT6_PHASE
C_MMCM1_CLKOUT6_PHASE
0.000000
C_MMCM1_CLKOUT0_USE_FINE_PS
C_MMCM1_CLKOUT0_USE_FINE_PS
false
C_MMCM1_CLKOUT1_USE_FINE_PS
C_MMCM1_CLKOUT1_USE_FINE_PS
false
C_MMCM1_CLKOUT2_USE_FINE_PS
C_MMCM1_CLKOUT2_USE_FINE_PS
false
C_MMCM1_CLKOUT3_USE_FINE_PS
C_MMCM1_CLKOUT3_USE_FINE_PS
false
C_MMCM1_CLKOUT4_USE_FINE_PS
C_MMCM1_CLKOUT4_USE_FINE_PS
false
C_MMCM1_CLKOUT5_USE_FINE_PS
C_MMCM1_CLKOUT5_USE_FINE_PS
false
C_MMCM1_CLKOUT6_USE_FINE_PS
C_MMCM1_CLKOUT6_USE_FINE_PS
false
C_MMCM1_COMPENSATION
C_MMCM1_COMPENSATION
ZHOLD
C_MMCM1_DIVCLK_DIVIDE
C_MMCM1_DIVCLK_DIVIDE
1
C_MMCM1_REF_JITTER1
C_MMCM1_REF_JITTER1
0.010000
C_MMCM1_CLKIN1_BUF
C_MMCM1_CLKIN1_BUF
false
C_MMCM1_CLKFBOUT_BUF
C_MMCM1_CLKFBOUT_BUF
false
C_MMCM1_CLOCK_HOLD
C_MMCM1_CLOCK_HOLD
false
C_MMCM1_STARTUP_WAIT
C_MMCM1_STARTUP_WAIT
false
C_MMCM1_EXT_RESET_HIGH
C_MMCM1_EXT_RESET_HIGH
1
C_MMCM1_FAMILY
C_MMCM1_FAMILY
virtex6
C_MMCM1_CLKOUT0_BUF
C_MMCM1_CLKOUT0_BUF
false
C_MMCM1_CLKOUT1_BUF
C_MMCM1_CLKOUT1_BUF
false
C_MMCM1_CLKOUT2_BUF
C_MMCM1_CLKOUT2_BUF
false
C_MMCM1_CLKOUT3_BUF
C_MMCM1_CLKOUT3_BUF
false
C_MMCM1_CLKOUT4_BUF
C_MMCM1_CLKOUT4_BUF
false
C_MMCM1_CLKOUT5_BUF
C_MMCM1_CLKOUT5_BUF
false
C_MMCM1_CLKOUT6_BUF
C_MMCM1_CLKOUT6_BUF
false
C_MMCM1_CLKIN1_MODULE
C_MMCM1_CLKIN1_MODULE
NONE
C_MMCM1_CLKIN1_PORT
C_MMCM1_CLKIN1_PORT
NONE
C_MMCM1_CLKFBIN_MODULE
C_MMCM1_CLKFBIN_MODULE
NONE
C_MMCM1_CLKFBIN_PORT
C_MMCM1_CLKFBIN_PORT
NONE
C_MMCM1_RST_MODULE
C_MMCM1_RST_MODULE
NONE
C_MMCM2_BANDWIDTH
C_MMCM2_BANDWIDTH
OPTIMIZED
C_MMCM2_CLKFBOUT_MULT_F
C_MMCM2_CLKFBOUT_MULT_F
1.000000
C_MMCM2_CLKFBOUT_PHASE
C_MMCM2_CLKFBOUT_PHASE
0.000000
C_MMCM2_CLKFBOUT_USE_FINE_PS
C_MMCM2_CLKFBOUT_USE_FINE_PS
false
C_MMCM2_CLKIN1_PERIOD
C_MMCM2_CLKIN1_PERIOD
0.000000
C_MMCM2_CLKOUT0_DIVIDE_F
C_MMCM2_CLKOUT0_DIVIDE_F
1.000000
C_MMCM2_CLKOUT0_DUTY_CYCLE
C_MMCM2_CLKOUT0_DUTY_CYCLE
0.500000
C_MMCM2_CLKOUT0_PHASE
C_MMCM2_CLKOUT0_PHASE
0.000000
C_MMCM2_CLKOUT1_DIVIDE
C_MMCM2_CLKOUT1_DIVIDE
1
C_MMCM2_CLKOUT1_DUTY_CYCLE
C_MMCM2_CLKOUT1_DUTY_CYCLE
0.500000
C_MMCM2_CLKOUT1_PHASE
C_MMCM2_CLKOUT1_PHASE
0.000000
C_MMCM2_CLKOUT2_DIVIDE
C_MMCM2_CLKOUT2_DIVIDE
1
C_MMCM2_CLKOUT2_DUTY_CYCLE
C_MMCM2_CLKOUT2_DUTY_CYCLE
0.500000
C_MMCM2_CLKOUT2_PHASE
C_MMCM2_CLKOUT2_PHASE
0.000000
C_MMCM2_CLKOUT3_DIVIDE
C_MMCM2_CLKOUT3_DIVIDE
1
C_MMCM2_CLKOUT3_DUTY_CYCLE
C_MMCM2_CLKOUT3_DUTY_CYCLE
0.500000
C_MMCM2_CLKOUT3_PHASE
C_MMCM2_CLKOUT3_PHASE
0.000000
C_MMCM2_CLKOUT4_DIVIDE
C_MMCM2_CLKOUT4_DIVIDE
1
C_MMCM2_CLKOUT4_DUTY_CYCLE
C_MMCM2_CLKOUT4_DUTY_CYCLE
0.500000
C_MMCM2_CLKOUT4_PHASE
C_MMCM2_CLKOUT4_PHASE
0.000000
C_MMCM2_CLKOUT4_CASCADE
C_MMCM2_CLKOUT4_CASCADE
false
C_MMCM2_CLKOUT5_DIVIDE
C_MMCM2_CLKOUT5_DIVIDE
1
C_MMCM2_CLKOUT5_DUTY_CYCLE
C_MMCM2_CLKOUT5_DUTY_CYCLE
0.500000
C_MMCM2_CLKOUT5_PHASE
C_MMCM2_CLKOUT5_PHASE
0.000000
C_MMCM2_CLKOUT6_DIVIDE
C_MMCM2_CLKOUT6_DIVIDE
1
C_MMCM2_CLKOUT6_DUTY_CYCLE
C_MMCM2_CLKOUT6_DUTY_CYCLE
0.500000
C_MMCM2_CLKOUT6_PHASE
C_MMCM2_CLKOUT6_PHASE
0.000000
C_MMCM2_CLKOUT0_USE_FINE_PS
C_MMCM2_CLKOUT0_USE_FINE_PS
false
C_MMCM2_CLKOUT1_USE_FINE_PS
C_MMCM2_CLKOUT1_USE_FINE_PS
false
C_MMCM2_CLKOUT2_USE_FINE_PS
C_MMCM2_CLKOUT2_USE_FINE_PS
false
C_MMCM2_CLKOUT3_USE_FINE_PS
C_MMCM2_CLKOUT3_USE_FINE_PS
false
C_MMCM2_CLKOUT4_USE_FINE_PS
C_MMCM2_CLKOUT4_USE_FINE_PS
false
C_MMCM2_CLKOUT5_USE_FINE_PS
C_MMCM2_CLKOUT5_USE_FINE_PS
false
C_MMCM2_CLKOUT6_USE_FINE_PS
C_MMCM2_CLKOUT6_USE_FINE_PS
false
C_MMCM2_COMPENSATION
C_MMCM2_COMPENSATION
ZHOLD
C_MMCM2_DIVCLK_DIVIDE
C_MMCM2_DIVCLK_DIVIDE
1
C_MMCM2_REF_JITTER1
C_MMCM2_REF_JITTER1
0.010000
C_MMCM2_CLKIN1_BUF
C_MMCM2_CLKIN1_BUF
false
C_MMCM2_CLKFBOUT_BUF
C_MMCM2_CLKFBOUT_BUF
false
C_MMCM2_CLOCK_HOLD
C_MMCM2_CLOCK_HOLD
false
C_MMCM2_STARTUP_WAIT
C_MMCM2_STARTUP_WAIT
false
C_MMCM2_EXT_RESET_HIGH
C_MMCM2_EXT_RESET_HIGH
1
C_MMCM2_FAMILY
C_MMCM2_FAMILY
virtex6
C_MMCM2_CLKOUT0_BUF
C_MMCM2_CLKOUT0_BUF
false
C_MMCM2_CLKOUT1_BUF
C_MMCM2_CLKOUT1_BUF
false
C_MMCM2_CLKOUT2_BUF
C_MMCM2_CLKOUT2_BUF
false
C_MMCM2_CLKOUT3_BUF
C_MMCM2_CLKOUT3_BUF
false
C_MMCM2_CLKOUT4_BUF
C_MMCM2_CLKOUT4_BUF
false
C_MMCM2_CLKOUT5_BUF
C_MMCM2_CLKOUT5_BUF
false
C_MMCM2_CLKOUT6_BUF
C_MMCM2_CLKOUT6_BUF
false
C_MMCM2_CLKIN1_MODULE
C_MMCM2_CLKIN1_MODULE
NONE
C_MMCM2_CLKIN1_PORT
C_MMCM2_CLKIN1_PORT
NONE
C_MMCM2_CLKFBIN_MODULE
C_MMCM2_CLKFBIN_MODULE
NONE
C_MMCM2_CLKFBIN_PORT
C_MMCM2_CLKFBIN_PORT
NONE
C_MMCM2_RST_MODULE
C_MMCM2_RST_MODULE
NONE
C_MMCM3_BANDWIDTH
C_MMCM3_BANDWIDTH
OPTIMIZED
C_MMCM3_CLKFBOUT_MULT_F
C_MMCM3_CLKFBOUT_MULT_F
1.000000
C_MMCM3_CLKFBOUT_PHASE
C_MMCM3_CLKFBOUT_PHASE
0.000000
C_MMCM3_CLKFBOUT_USE_FINE_PS
C_MMCM3_CLKFBOUT_USE_FINE_PS
false
C_MMCM3_CLKIN1_PERIOD
C_MMCM3_CLKIN1_PERIOD
0.000000
C_MMCM3_CLKOUT0_DIVIDE_F
C_MMCM3_CLKOUT0_DIVIDE_F
1.000000
C_MMCM3_CLKOUT0_DUTY_CYCLE
C_MMCM3_CLKOUT0_DUTY_CYCLE
0.500000
C_MMCM3_CLKOUT0_PHASE
C_MMCM3_CLKOUT0_PHASE
0.000000
C_MMCM3_CLKOUT1_DIVIDE
C_MMCM3_CLKOUT1_DIVIDE
1
C_MMCM3_CLKOUT1_DUTY_CYCLE
C_MMCM3_CLKOUT1_DUTY_CYCLE
0.500000
C_MMCM3_CLKOUT1_PHASE
C_MMCM3_CLKOUT1_PHASE
0.000000
C_MMCM3_CLKOUT2_DIVIDE
C_MMCM3_CLKOUT2_DIVIDE
1
C_MMCM3_CLKOUT2_DUTY_CYCLE
C_MMCM3_CLKOUT2_DUTY_CYCLE
0.500000
C_MMCM3_CLKOUT2_PHASE
C_MMCM3_CLKOUT2_PHASE
0.000000
C_MMCM3_CLKOUT3_DIVIDE
C_MMCM3_CLKOUT3_DIVIDE
1
C_MMCM3_CLKOUT3_DUTY_CYCLE
C_MMCM3_CLKOUT3_DUTY_CYCLE
0.500000
C_MMCM3_CLKOUT3_PHASE
C_MMCM3_CLKOUT3_PHASE
0.000000
C_MMCM3_CLKOUT4_DIVIDE
C_MMCM3_CLKOUT4_DIVIDE
1
C_MMCM3_CLKOUT4_DUTY_CYCLE
C_MMCM3_CLKOUT4_DUTY_CYCLE
0.500000
C_MMCM3_CLKOUT4_PHASE
C_MMCM3_CLKOUT4_PHASE
0.000000
C_MMCM3_CLKOUT4_CASCADE
C_MMCM3_CLKOUT4_CASCADE
false
C_MMCM3_CLKOUT5_DIVIDE
C_MMCM3_CLKOUT5_DIVIDE
1
C_MMCM3_CLKOUT5_DUTY_CYCLE
C_MMCM3_CLKOUT5_DUTY_CYCLE
0.500000
C_MMCM3_CLKOUT5_PHASE
C_MMCM3_CLKOUT5_PHASE
0.000000
C_MMCM3_CLKOUT6_DIVIDE
C_MMCM3_CLKOUT6_DIVIDE
1
C_MMCM3_CLKOUT6_DUTY_CYCLE
C_MMCM3_CLKOUT6_DUTY_CYCLE
0.500000
C_MMCM3_CLKOUT6_PHASE
C_MMCM3_CLKOUT6_PHASE
0.000000
C_MMCM3_CLKOUT0_USE_FINE_PS
C_MMCM3_CLKOUT0_USE_FINE_PS
false
C_MMCM3_CLKOUT1_USE_FINE_PS
C_MMCM3_CLKOUT1_USE_FINE_PS
false
C_MMCM3_CLKOUT2_USE_FINE_PS
C_MMCM3_CLKOUT2_USE_FINE_PS
false
C_MMCM3_CLKOUT3_USE_FINE_PS
C_MMCM3_CLKOUT3_USE_FINE_PS
false
C_MMCM3_CLKOUT4_USE_FINE_PS
C_MMCM3_CLKOUT4_USE_FINE_PS
false
C_MMCM3_CLKOUT5_USE_FINE_PS
C_MMCM3_CLKOUT5_USE_FINE_PS
false
C_MMCM3_CLKOUT6_USE_FINE_PS
C_MMCM3_CLKOUT6_USE_FINE_PS
false
C_MMCM3_COMPENSATION
C_MMCM3_COMPENSATION
ZHOLD
C_MMCM3_DIVCLK_DIVIDE
C_MMCM3_DIVCLK_DIVIDE
1
C_MMCM3_REF_JITTER1
C_MMCM3_REF_JITTER1
0.010000
C_MMCM3_CLKIN1_BUF
C_MMCM3_CLKIN1_BUF
false
C_MMCM3_CLKFBOUT_BUF
C_MMCM3_CLKFBOUT_BUF
false
C_MMCM3_CLOCK_HOLD
C_MMCM3_CLOCK_HOLD
false
C_MMCM3_STARTUP_WAIT
C_MMCM3_STARTUP_WAIT
false
C_MMCM3_EXT_RESET_HIGH
C_MMCM3_EXT_RESET_HIGH
1
C_MMCM3_FAMILY
C_MMCM3_FAMILY
virtex6
C_MMCM3_CLKOUT0_BUF
C_MMCM3_CLKOUT0_BUF
false
C_MMCM3_CLKOUT1_BUF
C_MMCM3_CLKOUT1_BUF
false
C_MMCM3_CLKOUT2_BUF
C_MMCM3_CLKOUT2_BUF
false
C_MMCM3_CLKOUT3_BUF
C_MMCM3_CLKOUT3_BUF
false
C_MMCM3_CLKOUT4_BUF
C_MMCM3_CLKOUT4_BUF
false
C_MMCM3_CLKOUT5_BUF
C_MMCM3_CLKOUT5_BUF
false
C_MMCM3_CLKOUT6_BUF
C_MMCM3_CLKOUT6_BUF
false
C_MMCM3_CLKIN1_MODULE
C_MMCM3_CLKIN1_MODULE
NONE
C_MMCM3_CLKIN1_PORT
C_MMCM3_CLKIN1_PORT
NONE
C_MMCM3_CLKFBIN_MODULE
C_MMCM3_CLKFBIN_MODULE
NONE
C_MMCM3_CLKFBIN_PORT
C_MMCM3_CLKFBIN_PORT
NONE
C_MMCM3_RST_MODULE
C_MMCM3_RST_MODULE
NONE
C_CLKIN_FREQ
Input Clock Frequency (Hz)
100000000
C_CLKFBIN_FREQ
Required Frequency (Hz)
0
C_CLKFBIN_DESKEW
Clock Deskew
NONE
C_PSDONE_GROUP
Variable Phase Shift
NONE
C_CLKOUT0_FREQ
Required Frequency (Hz)
125000000
C_CLKOUT0_PHASE
Required Phase
0
C_CLKOUT0_GROUP
Required Group
NONE
C_CLKOUT0_BUF
Buffered
TRUE
C_CLKOUT0_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT1_FREQ
Required Frequency (Hz)
0
C_CLKOUT1_PHASE
Required Phase
0
C_CLKOUT1_GROUP
Required Group
NONE
C_CLKOUT1_BUF
Buffered
TRUE
C_CLKOUT1_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT2_FREQ
Required Frequency (Hz)
0
C_CLKOUT2_PHASE
Required Phase
0
C_CLKOUT2_GROUP
Required Group
NONE
C_CLKOUT2_BUF
Buffered
TRUE
C_CLKOUT2_VARIABLE_PHASE
Varaible Phase
FALSE
C_CLKOUT3_FREQ
Required Frequency (Hz)
0
C_CLKOUT3_PHASE
Required Phase
0
C_CLKOUT3_GROUP
Required Group
NONE
C_CLKOUT3_BUF
Buffered
TRUE
C_CLKOUT3_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT4_FREQ
Required Frequency (Hz)
0
C_CLKOUT4_PHASE
Required Phase
0
C_CLKOUT4_GROUP
Required Group
NONE
C_CLKOUT4_BUF
Buffered
TRUE
C_CLKOUT4_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT5_FREQ
Required Frequency (Hz)
0
C_CLKOUT5_PHASE
Required Phase
0
C_CLKOUT5_GROUP
Required Group
NONE
C_CLKOUT5_BUF
Buffered
TRUE
C_CLKOUT5_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT6_FREQ
Required Frequency (Hz)
0
C_CLKOUT6_PHASE
Required Phase
0
C_CLKOUT6_GROUP
Required Group
NONE
C_CLKOUT6_BUF
Buffered
TRUE
C_CLKOUT6_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT7_FREQ
Required Frequency (Hz)
0
C_CLKOUT7_PHASE
Required Phase
0
C_CLKOUT7_GROUP
Required Group
NONE
C_CLKOUT7_BUF
Buffered
TRUE
C_CLKOUT7_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT8_FREQ
Required Frequency (Hz)
0
C_CLKOUT8_PHASE
Required Phase
0
C_CLKOUT8_GROUP
Required Group
NONE
C_CLKOUT8_BUF
Buffered
TRUE
C_CLKOUT8_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT9_FREQ
Required Frequency (Hz)
0
C_CLKOUT9_PHASE
Required Phase
0
C_CLKOUT9_GROUP
Required Group
NONE
C_CLKOUT9_BUF
Buffered
TRUE
C_CLKOUT9_VARIABLE_PHASE
Varaible Phase
FALSE
C_CLKOUT10_FREQ
Required Frequency (Hz)
0
C_CLKOUT10_PHASE
Required Phase
0
C_CLKOUT10_GROUP
Required Group
NONE
C_CLKOUT10_BUF
Buffered
TRUE
C_CLKOUT10_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT11_FREQ
Required Frequency (Hz)
0
C_CLKOUT11_PHASE
Required Phase
0
C_CLKOUT11_GROUP
Required Group
NONE
C_CLKOUT11_BUF
Buffered
TRUE
C_CLKOUT11_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT12_FREQ
Required Frequency (Hz)
0
C_CLKOUT12_PHASE
Required Phase
0
C_CLKOUT12_GROUP
Required Group
NONE
C_CLKOUT12_BUF
Buffered
TRUE
C_CLKOUT12_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT13_FREQ
Required Frequency (Hz)
0
C_CLKOUT13_PHASE
Required Phase
0
C_CLKOUT13_GROUP
Required Group
NONE
C_CLKOUT13_BUF
Buffered
TRUE
C_CLKOUT13_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT14_FREQ
Required Frequency (Hz)
0
C_CLKOUT14_PHASE
Required Phase
0
C_CLKOUT14_GROUP
Required Group
NONE
C_CLKOUT14_BUF
Buffered
TRUE
C_CLKOUT14_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKOUT15_FREQ
Required Frequency (Hz)
0
C_CLKOUT15_PHASE
Required Phase
0
C_CLKOUT15_GROUP
Required Group
NONE
C_CLKOUT15_BUF
Buffered
TRUE
C_CLKOUT15_VARIABLE_PHASE
Variable Phase
FALSE
C_CLKFBOUT_FREQ
Required Frequency (Hz)
0
C_CLKFBOUT_PHASE
C_CLKFBOUT_PHASE
0
C_CLKFBOUT_GROUP
Required Group
NONE
C_CLKFBOUT_BUF
Buffered
TRUE
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slice LUTs 1 28800 0
LUT Flip Flop pairs used 1 NA NA
fully used LUT-FF pairs 0 1 0
unique control sets 0 NA NA
IOs 25 NA NA
bonded IOBs 0 440 0
BUFG/BUFGCTRLs 2 32 6
PLL_ADVs 1 6 16




Timing Information TOP


Post Synthesis Clock Limits
These are the post synthesis clock frequencies. The critical frequencies are marked with green.
The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system.
MODULE CLK Port MAX FREQ
microblaze_0 DCACHE_FSL_OUT_CLK 176.616MHz
microblaze_0 DBG_CLK 176.616MHz
microblaze_0 DBG_UPDATE 176.616MHz
mdm_0 mdm_0/update 200.562MHz
mdm_0 SPLB_Clk 200.562MHz
mdm_0 mdm_0/drck_i 200.562MHz
my_custom_ip_register_0 SPLB_Clk 255.796MHz
RS232_Uart SPLB_Clk 310.849MHz
xps_intc_0 SPLB_Clk 317.360MHz
mb_plb PLB_Clk 324.781MHz
proc_sys_reset_0 Slowest_sync_clk 406.009MHz
SysACE_CompactFlash SPLB_Clk 408.497MHz
SysACE_CompactFlash SysACE_CLK 408.497MHz
ilmb LMB_Clk 529.381MHz
dlmb LMB_Clk 529.381MHz