ip_testing_mod Project Status (06/04/2010 - 22:45:35)
Project File: ip_testing_mod.xise Parser Errors: No Errors
Module Name: ip_testing_mod Implementation State: Synthesized
Target Device: xc5vlx50-1ff676
  • Errors:
No Errors
Product Version:ISE 12.1
  • Warnings:
279 Warnings (279 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 134 28800 0%
Number of Slice LUTs 118 28800 0%
Number of fully used LUT-FF pairs 69 183 37%
Number of bonded IOBs 232 440 52%
Number of BUFG/BUFGCTRLs 1 32 3%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Jun 4 22:45:35 20100279 Warnings (279 new)6 Infos (6 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 06/04/2010 - 22:45:35