my_custom_ip_register Project Status | |||
Project File: | my_custom_ip_register.xise | Parser Errors: | No Errors |
Module Name: | my_custom_ip_register | Implementation State: | Synthesized |
Target Device: | xc5vlx50-1ff676 |
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No Errors |
Product Version: | ISE 12.1 |
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406 Warnings (1 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 121 | 28800 | 0% | |
Number of Slice LUTs | 100 | 28800 | 0% | |
Number of fully used LUT-FF pairs | 48 | 173 | 27% | |
Number of bonded IOBs | 230 | 440 | 52% | |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue Jun 8 21:54:20 2010 | 0 | 406 Warnings (1 new) | 4 Infos (0 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |