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dc.contributor.authorGamarra, David Fosca
dc.contributor.authorKjeldsberg, Per Gunnar
dc.contributor.authorSundbeck, Henrik Valø
dc.date.accessioned2024-03-08T12:37:04Z
dc.date.available2024-03-08T12:37:04Z
dc.date.created2024-01-14T11:34:45Z
dc.date.issued2023
dc.identifier.citation2023 IEEE Nordic Circuits and Systems Conference (NorCAS)en_US
dc.identifier.isbn979-8-3503-3757-0
dc.identifier.urihttps://hdl.handle.net/11250/3121593
dc.description.abstractLens flare artifacts are undesired visual distortions caused by stray light, which can negatively impact the integrity and quality of an image. These artifacts pose a significant challenge in industrial applications like automotive and surveillance, where the quality and reliability of input images from cameras are crucial. Artificial intelligence, particularly deep learning neural networks, have shown promising results in attenuating lens flare. In this work, a synthetic flare dataset is generated, and an iterative training process that includes evaluation of transfer learning is employed to develop FlareNet, the first compact and lightweight U-Net based model for lens flare reduction. The FlareNet architecture, with less than 150,000 parameters comprising convolutional layers, demonstrates improvement in image quality by reducing flare artifacts on synthetic test images and real-life images, indicating its potential for achieving visually satisfactory results despite having less than 0.5% of the weights of the state-of-the-art neural architecture used for this same application. To demonstrate the viability of using a model such as FlareNet as a hardware accelerator, the neural network is implemented in C++ using Vitis HLS. Synthesis and validation are performed using the Vitis tool, and reports are analyzed while experimenting with HLS optimization directives. Resource utilization of less than 20% on a Zeus Zynq UltraScale FPGA is shown but further work is needed to optimize the design for real-time applications and effectively deploy the solution on an FPGA.en_US
dc.description.abstractLens Flare Attenuation Accelerator Design with Deep Learning and High-Level Synthesisen_US
dc.language.isoengen_US
dc.publisherIEEEen_US
dc.relation.ispartofProceedings of the 2023 IEEE Nordic Circuits and Systems Conference (NorCAS)
dc.titleLens Flare Attenuation Accelerator Design with Deep Learning and High-Level Synthesisen_US
dc.title.alternativeLens Flare Attenuation Accelerator Design with Deep Learning and High-Level Synthesisen_US
dc.typeChapteren_US
dc.typeConference objecten_US
dc.description.versionacceptedVersionen_US
dc.rights.holder© 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en_US
dc.identifier.doi10.1109/NorCAS58970.2023.10305455
dc.identifier.cristin2225988
cristin.ispublishedtrue
cristin.fulltextpostprint


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